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| 1. description the M37225M6-XXXSP, m37225m8-xxxsp, and m37225ecsp are single-chip microcomputers designed with cmos silicon gate tech- nology. they have a osd, i 2 c-bus interface, pwm output, and 12 v withstand, so it is useful for a channel selection system for tv. the features of the m37225ecsp are similar to those of the M37225M6-XXXSP except that the chip has a built-in prom which can be written electrically. the difference between M37225M6-XXXSP and m37225m8-xxxsp are the rom size. accordingly, the follow- ing descriptions will be for the M37225M6-XXXSP. 2. features l number of basic instructions .................................................... 71 l memory size rom ..................... 24k bytes (M37225M6-XXXSP) 32k bytes (m37225m8-xxxsp) 48k bytes (m37225ecsp) ram ...................... 1024 bytes (M37225M6-XXXSP, m37225m8-xxxsp) 2048 bytes (m37225ecsp) (*rom correction memory included) l minimum instruction execution time ......................................... 0.5 m s (at 8 mhz oscillation frequency) l power source voltage ................................................. 5 v 10 % l subroutine nesting ............................................. 128 levels (max.) l interrupts ....................................................... 16 types, 16 vectors l 8-bit timers .................................................................................. 4 l programmable i/o ports (ports p0, p1, p2, p3 0 Cp3 2 , p3 5 ) ..... 28 l input ports (ports p3 3 , p3 4 , p5 0 , p5 1 ) ........................................ 4 l output ports (ports p5 2 Cp5 5 ) ..................................................... 4 l 12 v withstand ports ................................................................... 6 l led drive ports ........................................................................... 4 l serial i/o ............................................................ 8-bit 5 1 channel l multi-master i 2 c-bus interface .............................. 1 (2 systems) l a-d converter (8-bit resolution) .................................... 8 channels l pwm output circuit ........................................ 14-bit 5 2, 8-bit 5 6 l power dissipation in operating ...................................................................... 165 mw (at v cc = 5.5v, 8 mhz oscillation frequency, and osd on) l rom correction function ................................................ 3 vectors l immediate return mode from wait state single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller M37225M6-XXXSP, m37225m8-xxxsp m37225ecsp mitsubishi microcomputers l osd function display characters ............................................... 24 characters 5 2 lines (it is possible to display 3 lines or more by software) kinds of characters ......... 381 kinds character display area 16 5 20 dots kinds of character sizes .............................. block display: 3 kinds sprite display: 1 kinds kinds of character colors. ................................. 8 colors (r, g, b) coloring unit ................... character, character background, raster display position horizontal: 64 levels vertical :255 levels attribute ........ border (all-bordered, shadow-bordered), button sprite display function wallpaper function window function corresponding to bi-scan mode 3. application tv rev. 1.1
2 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 table of contents 1. description .......................................................................... 1 2. feautures ............................................................................. 1 3. application ............................................................................ 1 4. pin configuration .............................................................. 3 5. functional block diagram ............................................. 4 6. performance overview ................................................... 5 7. pin description ................................................................... 7 8. functional description ................................................. 11 8.1 central processing unit (cpu) .................... 11 8.2 memory .................................................................. 12 8.3 interrupts ........................................................... 19 8.4 timers ..................................................................... 24 8.5 serial i/o ................................................................ 27 8.6 multi-master i 2 c-bus interface .................... 31 8.7 pwm output circuit .......................................... 44 8.8 a-d comparator .................................................. 49 8.9 rom correction function ............................. 53 8.10 osd functions ................................................... 54 (1) clock for osd .................................................... 57 (2) scan mode ......................................................... 58 (3) osd input/output pin control .............................. 59 8.10.1 block display .................................................... 60 (1) display position .................................................. 61 (2) dot size .............................................................. 65 (3) memory for osd ............................................... 66 (4) character color .................................................. 69 (5) character background color .............................. 69 (6) out1, out2 signals ......................................... 69 (7) attribute .............................................................. 72 (8) multiple display .................................................. 76 (9) window function ................................................ 77 8.10.2 sprite display ................................................ 80 8.10.3 raster display ................................................... 83 8.11. software runaway detect function ...... 85 8.12. reset circuit .................................................... 86 8.13. clock generating circuit ........................... 87 8.14. display oscillation circuit ........................ 88 8.15. auto-clear circuit ......................................... 88 8.16. addressing mode ............................................ 88 8.17. machine instructions ................................... 88 9. programming notes ........................................................ 88 10. absolute maximum ratings ......................................... 89 11. recommended operating conditions ..................... 89 12. electric characteristics .......................................... 90 13. a-d comparison characteristics ............................. 92 14. multi-master i 2 c-bus bus line characteristics ........... 92 15. prom programming method ....................................... 93 16. data required for mask orders .............................. 94 17. mask confirmation form ............................................. 95 18. mark specification form ........................................... 101 19. one time prom versions m37225ecsp marking ... 102 20. appendix ........................................................................... 103 21. package outline ........................................................... 131 3 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 4. pin configuration outline 42p4b fig. 4.1 pin configuration (top view) p 0 6 / i n t 2 / a - d 4 x o u t h s y n c / p 5 0 v s y n c / p 5 1 p 0 0 / p w m 0 p 0 1 / p w m 1 p 0 2 / p w m 2 p 0 3 / p w m 3 p 0 4 / p w m 4 p 0 5 / p w m 5 p 0 7 / i n t 1 p 2 3 / t i m 3 p 2 4 / t i m 2 p 2 5 p 2 6 p 2 7 d a 1 / p 3 5 p 3 2 / a - d 7 c n v s s x i n v s s 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 r e s e t r / p 5 2 g / p 5 3 b / p 5 4 o u t 1 / p 5 5 p 2 0 / s c l k p 2 1 / s o u t ( /s i n ) p 2 2 / s i n p 1 0 / ou t 2 / a - d 8 p 1 1 / s c l 1 p 1 2 / s c l 2 p 1 3 / s d a 1 p 1 4 / s d a 2 p 1 6 / a - d 2 p 3 0 / a - d 5 p 3 1 / a - d 6 o s c 1 / p 3 3 o s c 2 / p 3 4 v c c p 1 7 / d a 2 /a - d3 p 1 5 / i n t 3 / a - d 1 m 3 7 2 2 5 m 6 - x x x s p m 3 7 2 2 5 m 8 - x x x s p m 3 7 2 2 5 e c s p 4 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 5. functional block diagram fig. 5.1 functional block diagram of m37225 o u t 1 c l o c k i n p u t c l o c k o u t p u t x i n x o u t r e s e t i n p u t v c c v s s c n v s s i n p u t p o r t s p 3 3 , p 3 4 o s c 1 o s c 2 c l o c k i n p u t f o r o s d p w m 5 p w m 4 p w m 3 p w m 2 p w m 1 p w m 0 p 5 ( 6 ) b g r h s y n c v s y n c 1 4 - b i t p w m c i r c u i t 1 8 - b i t p w m c i r c u i t a c c u m u l a t o r a ( 8 ) t i m e r 4 t 4 ( 8 ) t i m e r 3 t 3 ( 8 ) t i m e r 2 t 2 ( 8 ) t i m e r 1 t 1 ( 8 ) t i m e r c o u n t s o u r c e s e l e c t i o n c i r c u i t t i m 2 t i m 3 i n s t r u c t i o n r e g i s t e r ( 8 ) i n s t r u c t i o n d e c o d e r c o n t r o l s i g n a l o s d c i r c u i t s t a c k p o i n t e r s ( 8 ) i n d e x r e g i s t e r x ( 8 ) p r o c e s s o r s t a t u s r e g i s t e r p s ( 8 ) 8 - b i t a r i t h m e t i c a n d l o g i c a l u n i t r o m p r o g r a m c o u n t e r p c l ( 8 ) p r o g r a m c o u n t e r p c h ( 8 ) r a m d a t a b u s c l o c k g e n e r a t i n g c i r c u i t r e s e t o u t p u t p o r t s p 5 2 Cp 5 5 o s d o u t p u t a d d r e s s b u s s i / o ( 8 ) s i n s c l k s o u t i n t 2 i n t 1 i n t 3 i / o p o r t s p 3 0 Cp 3 2 , p 3 5 1 7 2 6 2 7 1 6 p 3 ( 6 ) 3 9 4 0 4 1 4 2 2 1 2 0 1 9 2 5 2 2 2 1 1 8 2 4 2 3 i n d e x r e g i s t e r y ( 8 ) m u l t i - m a s t e r i 2 c - b u s i n t e r f a c e r o m c o r r e c t i o n f u n c t i o n s y n c s i g n a l i n p u t i n p u t p o r t s p 5 0 , p 5 1 s d a 2 s d a 1 s c l 2 s c l 1 a - d c o n v e r t e r 1 0 9 8 7 6 5 4 3 i / o p o r t p 0 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 p 1 ( 8 ) i / o p o r t p 1 1 5 1 4 1 3 1 2 1 1 3 6 3 7 3 8 p 2 ( 8 ) i / o p o r t p 2 p 0 ( 8 ) 1 4 - b i t p w m c i r c u i t 2 o u t 2 c l o c k o u t p u t f o r o s d 5 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 number of basic instructions instruction execution time clock frequency memory size input/output ports serial i/o multi-master i 2 c-bus interface a-d converter pwm output circuit timers rom correction function subroutine nesting interrupt clock generating circuit rom ram osd rom osd ram p0 0 Cp0 5 p0 6 , p0 7 p1 p2 p3 0 , p3 1 , p3 5 p3 2 p3 3 , p3 4 p5 0 , p5 1 p5 2 Cp5 5 i/o i/o i/o i/o i/o i/o input input output 71 0.5 m s (the minimum instruction execution time, at 8 mhz oscillation fre- quency) 8 mhz (maximum) 24k bytes 32k bytes 48k bytes 1024 bytes (rom correction memory included) 2048 bytes (rom correction memory included) 15k bytes 96 bytes 6-bit 5 1 (n-channel open-drain output structure, can be used as pwm output pins) 2-bit 5 1 (n-channel open-drain output structure, can be used as int input pins, a-d input pin) 8-bit 5 1 (cmos input/output structure, can be used as osd output pin, int input pin, a-d input pins, da output pin, multi-master i 2 c-bus interface) 8-bit 5 1 (cmos input/output structure, can be used as serial i/o pins, timer external clock input pins) 3-bit 5 1 (cmos output structure, or n-channel open-drain output struc- ture, can be used as a-d input pins, da output pin) 1-bit 5 1 (n-channel open-drain output structure, can be used as a-d input pin) 2-bit 5 1 (can be used as osd clock input/output pins) 2-bit 5 1 (n-channel open-drain output structure, can be used as horizonal ? vertical synchronous sibnal input pins) 4-bit 5 1 (cmos output structure, can be used as osd output pins) 8-bit 5 1 1 (2 systems) 8 channels (8-bit resolution) 14-bit 5 2, 8-bit 5 6 8-bit timer 5 4 3 vectors 128 levels (maximum) <16 types> int external interrupt 5 3, internal timer interrupt 5 6, serial i/o interrupt 5 1, osd interrupt 5 1, multi-master i 2 c-bus interface interrupt 5 1, f(x in )/4096 interrupt 5 1, sprite osd interrupt 5 1, a-d conversion inter- rupt 5 1, v sync interrupt 5 1, brk instruction interrupt 5 1, reset 5 1 2 built-in circuits (externally connected to a ceramic resonator or a quartz- crystal oscillator) parameter 6. performance overview M37225M6-XXXSP m37225m8-xxxsp m37225ecsp M37225M6-XXXSP, m37225m8-xxxsp m37225ecsp table 6.1 performance overview functions 6 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 power source voltage power dissipation number of display characters dot structure kinds of characters kinds of character sizes character font coloring display position functions table 6.2 performance overview (continued) osd function 24 characters 5 2 lines 16 5 20 dots 381 kinds 3 kinds 1 screen : 8 kinds (per character unit) horizontal : 64 levels, vertical : 255 levels 5v 10% 165 mw typ. ( at oscillation frequency f(x in ) = 8 mhz, f osc = 8 mhz) 110 mw typ. ( at oscillation frequency f(x in ) = 8 mhz) 1.65 mw ( maximum ) C10 c to 70 c cmos silicon gate process 42-pin plastic molded sdip parameter osd on osd off in stop mode operating temperature range device structure package 7 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 pin name input/ functions output v cc , power source apply voltage of 5 v 10 % to (typical) v cc , and 0 v to v ss . v ss cnv ss cnv ss this is connected to v ss . ______ reset reset input input to enter the reset state, the reset input pin must be kept at a low for 2 m s or more (under normal v cc conditions). if more time is needed for the quartz-crystal oscillator to stabilize, this low condition should be maintained for the required time. x in clock input input this chip has an internal clock generating circuit. to control generating frequency, an external ceramic resonator or a quartz-crystal oscillator is connected between pins x in and x out clock output output x out . if an external clock is used, the clock source should be connected to the x in pin and the x out pin should be left open. p0 0 /pwm0C i/o port p0 i/o port p0 is an 8-bit i/o port with direction register allowing each i/o bit to be individually p0 5 /pwm5 , programmed as input or output. at reset, this port is set to input mode. the output structure p0 6 /int2/a-d4, is n-channel open-drain output. (see note 1) p0 7 /int1 pwm output output pins p0 0 Cp0 5 are also used as pwm output pins pwm0Cpwm5 respectively. the output structure is n-channel open-drain output. external interrupt input pins p0 6 and p0 7 are also used as int external interrupt input pins int2 and int1 input respectively. analog input input p0 6 pin is also used as analog input pin a-d4. p1 0 /out2/a-d8, i/o port p1 i/o port p1 is an 8-bit i/o port and has basically the same functions as port p0. the p1 1 /scl1, output structure is cmos output. (see note 1) p1 2 /scl2, osd output output pins p1 0 is also used as osd output pin out2. the output structure is cmos output. p1 3 /sda1, multi-master i/o pins p1 1 Cp1 4 are used as scl1, scl2, sda1 and sda2 respectively, when multi-master p1 4 /sda2, i 2 c-bus interface i 2 c-bus interface is used. the output structure is n-channel open-drain output. p1 5 /int3/a-d1, analog input input pins p1 0 , p1 5 Cp1 7 are also used as analog input pin a-d8, a-d1Ca-d3 respectively. p1 6 /a-d2, external interrupt input p1 5 pin is also used as int external interrupt input pin int3. p1 7 /da2/a-d3 input da output output pins p1 7 is also used as 14-bit pwm output pin da2. the output structure is cmos output. p2 0 /s clk , i/o port p2 i/o port p2 is an 8-bit i/o port and has basically the same functions as port p0. the p2 1 /s out (/s in ), output structure is cmos output. (see note 1) p2 2 /s in , serial i/o synchronous i/o p2 0 pin is also used as serial i/o synchronous clock input/output pin s clk . the output p2 3 /tim3, clock input/output port structure is n-channel open-drain output. p2 4 /tim2, serial i/o data i/o p2 1 pin is also used as serial i/o data input/output pin s out (/s in ). the output p2 5 Cp2 7 input/output structure is n-channel open-drain output. serial i/o data input input p2 2 pin is also used as serial i/o data input pin s in . external clock input pins p2 3 and p2 4 are also used as timer external clock input pins tim3 and tim2 input for timer respectively. p3 0 /a-d5, i/o port p3 i/o ports p3 0 Cp3 2 and p3 5 are a 3-bit i/o port and has basically the same functions as port 0 p3 1 /a-d6, (see note 1). either cmos output or n-channel open-drain output structure can be selected p3 2 /a-d7, as ports p3 0 , p3 1 and p3 5 . the output structure of port p3 2 is n-channel da1/p3 5 open-drain output structure.(see notes 1, 2) analog input input pins p3 0 Cp3 2 are also used as analog input pins a-d5Ca-d7 respectively. da output output p3 5 pin is also used as 14-bit pwm output pin da1. the output structure is cmos output. at reset, output is undefined. osc1/p3 3 , input port p3 input pins p3 3 and p3 4 are a 2-bit input port. osc2/p3 4 , clock input for osd input p3 3 pin is also used as osd clock input pin osc1. clock output for osd output p3 4 pin is also used as osd clock output pin osc2. the output structure is cmos output. 7. pin description table 7.1 pin description 8 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 notes 1: port pi (i = 0 to 3) has the port pi direction register which can be used to program each bit as an input (0) or an output ( 1). the pins programmed as 1 in the direction register are output pins. when pins are programmed as 0, they are input pins. when pins are programmed as ou tput pins, the output data are written into the port latch and then output. when data is read from the output pins, the output pin level is not read but t he data of the port latch is read. this allows a previously-output value to be read correctly even if the output low voltage has risen, for example, because a lig ht emitting diode was directly driven. the input pins are in the floating state, so the values of the pins can be read. when data is written into the input pi n, it is written only into the port latch, while the pin remains in the floating state. 2: to switch output structures, set by the following bits. p3 0 : bit 6 of port p3 direction register p3 1 : bit 7 of port p3 direction register p3 5 : bit 5 of port p3 5 output mode control register when 0, cmos output; when 1, n-channel open-drain output. pin name input/ functions output h sync /p5 0 , input port p5 input ports p5 0 and p5 1 are a 2-bit input port. v sync /p5 1 h sync input input this is a horizontal synchronizing signal input for osd. v sync input input this is a vertical synchronizing signal input for osd. r/p5 2 , output port p5 output ports p5 2 Cp5 5 are a 4-bit output port. the output structure is cmos output. g/p5 3 , b/p5 4 , osd output output pins p5 2 Cp5 5 are also used as osd output pins r, g, b, out1 respectively. the output out1/p5 5 structure is cmos output. at reset, output is low. table 7.2 pin description (continued) 9 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 fig. 7.1 i/o pin block diagram (1) n-channel open-drain output ports p0 0 Cp0 5 note : each port is also used as follows : p0 0 Cp0 5 : pwm0Cpwm5 n-channel open-drain output ports p0 6 , p0 7 , p3 2 note : each port is also used as follows : p0 6 : int2/a-d4 p0 7 : int1 cmos output ports p1 , p2, p3 0 , p3 1 , p3 5 notes 1: each port is also used as follows : p1 0 : out2/ad8 p2 2 : s in p1 1 : scl1 p2 3 : tim3 p1 2 : scl2 p2 4 : tim2 p1 3 : sda1 p3 0 : a-d5 p1 4 : sda2 p3 1 : a-d6 p1 5 : int3/a-d1 p3 5 : da1 p1 6 : a-d2 p1 7 : da2/a-d3 p2 0 : s clk p2 1 : s out /(s in ) 2: either cmos output or n-channel open- drain output structure can be selected as ports p3 0 , p3 1 and p3 5 (when selecting n-channel open-drain, it is the same with n-channel open-drain output below). p o r t s p 1 , p 2 , p 3 0 , p 3 1 d a t a b u s p o r t s p 0 0 C p 0 5 d a t a b u s p o r t s p 0 6 , p 0 7 , p 3 2 d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h d i r e c t i o n r e g i s t e r p o r t l a t c h d i r e c t i o n r e g i s t e r p o r t l a t c h 10 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 p 5 0 , p 5 1 i n t e r n a l c i r c u i t d a t a b u s i n t e r n a l c i r c u i t p 5 2 C p 5 5 d a t a b u s p o r t l a t c h p 3 3 , p 3 4 d a t a b u s cmos output ports p5 2 Cp5 5 note : each pin is also used as follows : p5 2 : r p5 3 : g p5 4 : b p5 5 : out1 schmidt input ports p5 0 , p5 1 note : each pin is also used as follows : p5 0 : h sync p5 1 : v sync fig. 7.2 i/o pin block diagram (2) input ports p3 3 , p3 4 note : each pin is also used as follows : p3 3 : osc1 p3 4 : osc2 11 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 8. functional description 8.1 central processing unit (cpu) this microcomputer uses the standard 740 family instruction set. refer to the table of 740 family addressing modes and machine instructions or the series 740 12 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 8.2 memory 8.2.1 special function register (sfr) area the special function register (sfr) area in the zero page contains control registers such as i/o ports and timers. 8.2.2 ram ram is used for data storage and for stack area of subroutine calls and interrupts. 8.2.3 rom rom is used for storing user programs as well as the interrupt vector area. 8.2.4 osd ram ram for display is used for specifying the character codes and col- ors to display. 8.2.5 osd rom rom for display is used for storing character data. 8.2.6 interrupt vector area the interrupt vector area contains reset and interrupt vectors. 8.2.7 zero page the 256 bytes from addresses 0000 16 to 00ff 16 are called the zero page area. the internal ram and the special function registers (sfr) are allocated to this area. the zero page addressing mode can be used to specify memory and register addresses in the zero page area. access to this area with only 2 bytes is possible in the zero page addressing mode. 8.2.8 special page the 256 bytes from addresses ff00 16 to ffff 16 are called the spe- cial page area. the special page addressing mode can be used to specify memory addresses in the special page area. access to this area with only 2 bytes is possible in the special page addressing mode. 8.2.9 rom correction vector this is used as the program jump destination addresses for rom correction. 13 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 fig. 8.2.1 memory map (M37225M6-XXXSP, m37225m8-xxxsp) 0 0 0 0 1 6 0 0 c 0 1 6 0 0 f f 1 6 0 1 f f 1 6 s f r a r e a 0 2 1 7 1 6 0 2 1 d 1 6 0 2 4 0 1 6 0 2 e 0 1 6 0 1 0 0 1 6 0 2 4 f 1 6 0 2 c 0 1 6 r o m c o r r e c t i o n f u n c t i o n v e c t o r 1 : a d d r e s s 0 2 c 0 1 6 v e c t o r 2 : a d d r e s s 0 2 e 0 1 6 v e ct o r 3 : a d d r e s s 0 3 0 0 1 6 ? m 3 7 2 5 5 m 6 - x x x s p , m 3 7 2 5 5 m 8 - x x x s p ( 1 0 2 4 b y t e s ) 0 8 7 7 1 6 0 8 0 0 1 6 o s d r a m ( 9 6 b y r e s ) ( s e e n o t e ) 8 0 0 0 1 6 f f f f 1 6 f f d e 1 6 f f 0 0 1 6 i n t e r r u p t v e c t o r a r e a s p e c i a l p a g e a 0 0 0 1 6 m 3 7 2 2 5 m 8 - x x x s p ro m ( 3 2 k b y t e s ) m 3 7 2 2 5 m 6 - x x x s p r o m ( 2 4 k b y t e s ) 0 0 b f 1 6 n o t e : r e f e r t o t a b l e 8 . 1 0 . 3 o s d r a m . 1 0 0 0 0 1 6 1 3 b f f 1 6 1 1 4 0 0 1 6 1 5 4 f f 1 6 1 5 4 0 0 1 6 1 5 6 f f 1 6 1 5 6 0 0 1 6 o s d r o m ( 1 5 k b y t e s ) 1 f f f f 1 6 1 7 8 f f 1 6 1 7 8 0 0 1 6 1 7 a f f 1 6 1 7 a 0 0 1 6 1 5 8 f f 1 6 1 5 8 0 0 1 6 1 5 a f f 1 6 1 5 a 0 0 1 6 1 5 c f f 1 6 1 5 c 0 0 1 6 1 5 e f f 1 6 1 5 e 0 0 1 6 1 6 0 f f 1 6 1 6 0 0 0 1 6 1 6 2 f f 1 6 1 6 2 0 0 1 6 1 6 4 f f 1 6 1 6 4 0 0 1 6 1 6 6 f f 1 6 1 6 6 0 0 1 6 1 6 8 f f 1 6 1 6 8 0 0 1 6 1 6 a f f 1 6 1 6 a 0 0 1 6 1 6 c f f 1 6 1 6 c 0 0 1 6 1 6 e f f 1 6 1 6 e 0 0 1 6 1 7 0 f f 1 6 1 7 0 0 0 1 6 1 7 2 f f 1 6 1 7 2 0 0 1 6 1 7 4 f f 1 6 1 7 4 0 0 1 6 1 7 6 f f 1 6 1 7 6 0 0 1 6 0 4 f f 1 6 0 3 0 0 1 6 z e r o p a g e n o t u s e d 2 p a g e r e g i s t e r ( 1 ) n o t u s e d 2 p a g e r e g i s t e r ( 2 ) n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d 14 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 fig. 8.2.2 memory map (m37225ecsp) 0 0 0 0 1 6 0 0 c 0 1 6 0 0 f f 1 6 0 1 f f 1 6 s f r a r e a z e r o p a g e 0 2 1 7 1 6 0 2 1 d 1 6 0 2 4 0 1 6 0 1 0 0 1 6 0 2 4 f 1 6 4 0 0 0 1 6 f f f f 1 6 f f d e 1 6 f f 0 0 1 6 r o m ( 4 8 k b y t e ) r a m ( 2 0 4 8 b y t e s ) n o t e : r e f e r t o t a b l e 8 . 1 0 . 1 3 o s d r a m . 1 0 0 0 0 1 6 1 3 b f f 1 6 1 1 4 0 0 1 6 1 5 4 f f 1 6 1 5 4 0 0 1 6 1 5 6 f f 1 6 1 5 6 0 0 1 6 o s d r o m ( 1 5 k b y t e s ) 1 f f f f 1 6 1 7 8 f f 1 6 1 7 8 0 0 1 6 1 7 a f f 1 6 1 7 a 0 0 1 6 1 5 8 f f 1 6 1 5 8 0 0 1 6 1 5 a f f 1 6 1 5 a 0 0 1 6 1 5 c f f 1 6 1 5 c 0 0 1 6 1 5 e f f 1 6 1 5 e 0 0 1 6 1 6 0 f f 1 6 1 6 0 0 0 1 6 1 6 2 f f 1 6 1 6 2 00 1 6 1 6 4 f f 1 6 1 6 4 0 0 1 6 1 6 6 f f 1 6 1 6 6 0 0 1 6 1 6 8 f f 1 6 1 6 8 0 0 1 6 1 6 a f f 1 6 1 6 a 0 0 1 6 1 6 c f f 1 6 1 6 c 0 0 1 6 1 6 e f f 1 6 1 6 e 0 0 1 6 1 7 0 f f 1 6 1 7 0 0 0 1 6 1 7 2 f f 1 6 1 7 2 0 0 1 6 1 7 4 f f 1 6 1 7 4 0 0 1 6 1 7 6 f f 1 6 1 7 6 0 0 1 6 0 0 b f 1 6 ? m 3 7 2 5 5 e c s p 0 2 e 0 1 6 0 2 c 0 1 6 0 7 f f 1 6 0 3 0 0 1 6 0 8 7 7 1 6 0 8 0 0 1 6 0 9 0 0 1 6 0 9 f f 1 6 o s d r a m ( 9 6 b y t e s ) ( s e e n o t e ) n o t u s e d 2 p a g e r e g i s t e r ( 1 ) n o t u s e d 2 p a g e r e g i s t e r ( 2 ) n o t u s e d r o m c o r r e c t i o n f u n c t i o n v e c t o r 1 : a d d r e s s 0 2 c 0 1 6 v e c t o r 2 : a d d r e s s 0 2 e 0 1 6 v e c t o r 3 : a d d r e s s 0 3 0 0 1 6 n o t u s e d n o t u s e d i n t e r r u p t v e c t o r a r e a s p e c i a l p a g e n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d 15 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 fig. 8.2.3 memory map of special function register (sfr) (1) n s f r a r e a ( a d d r e s s e s c 0 1 6 t o d f 1 6 ) d 0 1 6 d 1 1 6 d 2 1 6 d 3 1 6 d 4 1 6 d 5 1 6 d 6 1 6 d 7 1 6 d 8 1 6 d 9 1 6 d a 1 6 d b 1 6 d c 1 6 d d 1 6 d e 1 6 d f 1 6 c 0 1 6 c 1 1 6 c 2 1 6 c 3 1 6 c 4 1 6 c 5 1 6 c 6 1 6 c 7 1 6 c 8 1 6 c 9 1 6 c b 1 6 c c 1 6 c d 1 6 c e 1 6 c f 1 6 c a 1 6 a d d r e s s p o r t p 5 ( p 5 ) o s d p o r t c o n t r o l r e g i s t e r ( p f ) d a 1 - h r e g i s t e r ( d a 1 - h ) d a 1 - l r e g i s t e r ( d a 1 - l ) p w m 0 r e g i s t e r ( p w m 0 ) p o r t p 1 ( p 1 ) p o r t p 1 d i r e c t i o n r e g i s t e r ( d 1 ) p o r t p 3 ( p 3 ) p o r t p 3 d i r e c t i o n r e g i s t e r ( d 3 ) p o r t p 2 ( p 2 ) p o r t p 2 d i r e c t i o n r e g i s t e r ( d 2 ) r e g i s t e r p o r t p 0 ( p 0 ) p o r t p 0 d i r e c t i o n r e g i s t e r ( d 0 ) p w m 1 r e g i s t e r ( p w m 1 ) p w m 2 r e g i s t e r ( p w m 2 ) p w m 3 r e g i s t e r ( p w m 3 ) p w m 4 r e g i s t e r ( p w m 4 ) p w m o u t p u t c o n t r o l r e g i s t e r 1 ( p w ) b 7 b 0 b i t a l l o c a t i o n s t a t e i m m e d i a t e l y a f t e r r e s e t ? 0 0 1 6 b 7 b 0 ? 0 0 1 6 ? 0 0 1 6 0 0 0 ? ? 0 0 0 0? ? ? ??? s e r i a l i / o m o d e r e g i s t e r ( s m ) s e r i a l i / o r e g i s t e r ( s i o ) 0 0 1 6 p o r t p3 5 o u t p u t m o d e c o n t r o l r e g i s t e r ( p 3 s ) t e s t r e g i s t e r i n t e r r u p t i n p u t p o l a r i t y r e g i s t e r ( i p ) p w m o u t p u t c o n t r o l r e g i s t e r 2 ( p n ) i 2 c d a t a s h i f t r e g i s t e r ( s 0 ) i 2 c c o n t r o l r e g i s t e r ( s 1 d ) i 2 c c l o c k c o n t r o l r e g i s t e r ( s 2 ) i 2 c s t a t u s r e g i s t e r ( s 1 ) i 2 c a d d r e s s r e g i s t e r ( s 0 d ) 0 a d c o n v e r s i o n r e g i s t e r ( a d ) a d c o n t r o l r e g i s t e r ( a d c o n ) p 5 2 s e l 00 p 5 3 s e l p 5 4 s e l p 5 5 s e l o u t 2 s e l 0 p 5 2 o u t p 5 3 o u t p 5 4 o u t p 5 5 o u t p 5 0 i n p 5 1 i n 0 0 p 3 5 s p 3 1 sp 3 0 sp 3 5 dp 3 2 dp 3 1 dp 3 0 d p 3 2p 3 1p 3 0 p 3 5 p 3 4 i np 3 3 i n ? ? 0 ? ? 0 0 ?? 0 p w 0 p w 1 p w 2 p w 3 p w 4 p w 5 p w 6 p w 7 p n 2 p n 3 p n 4 ? 0 0 ? ? ? ? ? ? ? ? ? ? 0 0 1 6 0 0 1 6 0 0 1 6 s a d 0 s a d 1 s a d 2 s a d 3 s a d 4 s a d 5 s a d 6 r b w l r b a d 0 a a s a l p i n b b t r x m s t b c 0 b c 1 b c 2 e s o a l s b s e l 0 b s e l 1 1 0 b i t s a d d 1 d 2 d 3 d 4 d 5 d 6 d 7d 0 p n 5 ? 00 00 11 0 0 p o l 3p o l 2p o l 1o c g 1o c g 0 01 1 0 0?? 0 ? 0 0 1 6 0 0 1 6 s m 0 s m 1 s m 2 s m 3 s m 5 s m 6 0 c c r 0 c c r 1 c c r 2 c c r 3 c c r 4 a c k f a s t m o d e a c k b i t a d i n 0 0 0 a d i n 1 a d i n 2 a d s t r a d v r e f ? 0 8 1 6 0 0 1 6 0 0 1 6 ? 0 0 ? 0 0 0 1 0 0 : f i x t o t h i s b i t t o 0 ( d o n o t w r i t e t o 1 ) : b i t a l l o c a t i o n s t a t e i m m e d i a t e l y a f t e r r e s e t f u n c t i o n b i t : n o f u n c t i o n b i t : f i x t o t h i s b i t t o 1 ( d o n o t w r i t e t o 0 ) n a m e : : 0 i m m e d i a t e l y a f t e r r e s e t : i n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t 0 1 ? : 1 i m m e d i a t e l y a f t e r r e s e t 1 0 16 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 fig. 8.2.4 memory map of special function register (sfr) (2) f 0 1 6 f 1 1 6 f 2 1 6 f 3 1 6 f 4 1 6 f 5 1 6 f 6 1 6 f 7 1 6 f 8 1 6 f 9 1 6 f a 1 6 f b 1 6 f c 1 6 f d 1 6 f e 1 6 f f 1 6 e 0 1 6 e 1 1 6 e 2 1 6 e 3 1 6 e 4 1 6 e 5 1 6 e 6 1 6 e 7 1 6 e 8 1 6 e 9 1 6 e b 1 6 e c 1 6 e d 1 6 e e 1 6 e f 1 6 e a 1 6 o s d c o n t r o l r e g i s t e r ( o c ) c o l o r r e g i s t e r 5 ( c o 5 ) c o l o r r e g i s t e r 7 ( c o 7 ) c o l o r r e g i s t e r 8 ( c o 8 ) t i m e r 1 ( t 1 ) b l o c k 2 v r e g i s t e r ( b 2 v p ) c o l o r r e g i s t e r 1 ( c o 1 ) c o l o r r e g i s t e r 2 ( c o 2 ) s p r i t e h r e g i s t e r ( s h p ) s p r i t e v r e g i s t e r ( s v p ) b l o c k h r e g i s t e r ( b h p ) b l o c k 1 v r e g i s t e r ( b 1 v p ) t i m e r 2 ( t 2 ) t i m e r 3 ( t 3 ) t i m e r 4 ( t 4 ) t i m e r m o d e r e g i s t e r 1 ( t m 1 ) t i m e r m o d e r e g i s t e r 2 ( t m 2 ) p w m 5 r e g i s t e r ( p w m 5 ) b l o c k 1 c o n t r o l r e g i s t e r ( b 1 c ) i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 ) i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) c o l o r r e g i s t e r 3 ( c o 3 ) c o l o r r e g i s t e r 4 ( c o 4 ) c o l o r r e g i s t e r 6 ( c o 6 ) c p u m o d e r e g i s t e r ( c m ) b 7 b 0 s c 0 s c 1 s c 2 s c 3 o c 0 o c 1 o c 2 t m 2 0 t m 2 1 t m 2 2 t m 2 3 t m 2 4 t m 1 0 t m 1 1 t m 1 2 t m 1 3 t m 1 4 c m 2 t m 1 r t m 2 r t m 3 r t m 4 r o s d r v s c r i t 3 r c k 0 m s r i t 1 r i t 2 r s 1 r t m 1 e t m 2 e t m 3 e t m 4 e o s d e v s c e i t 3 e i t 1 e i t 2 e s 1 e m s e t m 2 5 b 7 b 0 c k 0 ? ? ?? ??? ? 0 f f 1 6 0 7 1 6 f f 1 6 0 7 1 6 ? ? ? 00 ?? ? 00 t m 1 5 0 0 0 01 11 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0?? 3 c 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 s p r i t e c o n t r o l r e g i s t e r ( s c ) o s d i / o p o l a r i t y c o n t r o l r e g i s t e r ( o p c ) t e s t r e g i s t e r t e s t r e g i s t e r a d e a d r s p e s p r i i c r b 2 c 0 b 2 c 1 b 2 c 2 b 2 c 3 b 2 c 4 b 1 c 0 b 1 c 1 b 1 c 2 b 1 c 3 b 1 c 4 0 0 1 6 0 0 1 6 c k 0 00 ?? ? 0?? b l o c k 2 c o n t r o l r e g i s t e r ( b 2 c ) b h p 0 b h p 1 b h p 2 b h p 3 b h p 4 b h p 5 b 1 v p 0 b 1 v p 1 b 1 v p 2 b 1 v p 3 b 1 v p 4 b 1 v p 5 b 1 v p 6 b 1 v p 7 b 2 v p 0 b 2 v p 1 b 2 v p 2 b 2 v p 3 b 2 v p 4 b 2 v p 5 b 2 v p 6 b 2 v p 7 s c 4 s c 5 s c 6 s c 7 s h p 0 s h p 1 s h p 2 s h p 3 s h p 4 s h p 5 s h p 6 s v p 0 s v p 1 s v p 2 s v p 3 s v p 4 s v p 5 s v p 6 s v p 7 o c 3 o c 4 o c 5 o c 6 o c 7 o p c 0 o p c 1 o p c 2 o p c 3 o p c 4 o p c 5 o p c 6 o p c 7 c o 1 1 c o 1 2 c o 1 3 c o 1 5 c o 2 1 c o 2 2 c o 2 3 c o 2 5 c o 1 4 c o 2 4 c o 1 6 c o 2 6 c o 1 0 c o 2 0 c o 3 1 c o 3 2 c o 3 3 c o 3 5c o 3 4 c o 3 6c o 3 0 c o 4 1 c o 4 2 c o 4 3 c o 4 5c o 4 4 c o 4 6c o 4 0 c o 5 1 c o 5 2 c o 5 3 c o 5 5 c o 6 1 c o 6 2 c o 6 3 c o 6 5 c o 5 4 c o 6 4 c o 5 6 c o 6 6 c o 5 0 c o 6 0 c o 7 1 c o 7 2 c o 7 3 c o 7 5c o 7 4 c o 7 6c o 7 0 c o 8 1 c o 8 2 c o 8 3 c o 8 5c o 8 4 c o 8 6c o 8 0 ? ?? ??? ? 0 ? ?? ??? ? 0 ? ?? ??? ? 0 0 0 1 6 ? ?? ??? ? 0 ? ?? ??? ? 0 ? ?? ??? ? 0 ? ?? ??? ? 0 0 0 1 6 0 0 1 6 ? ? n s f r a r e a ( a d d r e s s e s e 0 1 6 t o f f 1 6 ) a d d r e s s r e g i s t e r b i t a l l o c a t i o ns t a t e i m m e d i a t e l y a f t e r r e s e t : f i x t o t h i s b i t t o 0 ( d o n o t w r i t e t o 1 ) : b i t a l l o c a t i o n s t a t e i m m e d i a t e l y a f t e r r e s e t f u n c t i o n b i t : n o f u n c t i o n b i t : f i x t o t h i s b i t t o 1 ( d o n o t w r i t e t o 0 ) n a m e : : 0 i m m e d i a t e l y a f t e r r e s e t : i n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t 0 1 ? : 1 i m m e d i a t e l y a f t e r r e s e t 1 0 i i c e s h p 7 17 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 fig. 8.2.5 memory map of 2 page register area b 7b 0b 7b 0 2 1 0 1 6 2 1 1 1 6 2 1 2 1 6 2 1 3 1 6 2 1 4 1 6 2 1 5 1 6 2 1 6 1 6 2 1 7 1 6 2 1 8 1 6 2 1 9 1 6 2 1 b 1 6 2 1 c 1 6 2 1 d 1 6 2 1 e 1 6 2 1 f 1 6 2 1 a 1 6 r o m c o r r e c t i o n e n a b l e r e g i s t e r ( r c r ) r o m c o r r e c t i o n a d d r e s s 1 ( h i g h - o r d e r ) r o m c o r r e c t i o n a d d r e s s 1 ( l o w - o r d e r ) ? ? ? ? r o m c o r r e c t i o n a d d r e s s 2 ( h i g h - o r d e r ) r o m c o r r e c t i o n a d d r e s s 2 ( l o w - o r d e r ) r c r 1r c r 0 ? ? ? ? ? 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 0 1 6 2 4 0 1 6 2 4 1 1 6 2 4 2 1 6 2 4 3 1 6 ? ? 2 4 4 1 6 2 4 6 1 6 2 4 5 1 6 l e f t b o r d e r c o n t r o l r e g i s t e r ( l b r ) b b r 0 2 4 7 1 6 2 4 9 1 6 2 4 8 1 6 t e s t r e g i s t e r 0 0 1 6 2 4 a 1 6 ? ? 0 0? ? ? ? 2 4 b 1 6 2 4 c 1 6 ? 2 4 e 1 6 2 4 d 1 6 2 4 f 1 6 ? ? ? r i g h t b o r d e r c o n t r o l r e g i s t e r ( r b r ) t o p b o r d e r c o n t r o l r e g i s t e r ( t b r ) b o t t o m b o r d e r c o n t r o l r e g i s t e r ( b b r ) 0 0 1 6 b b r 1 b b r 2 b b r 3 b b r 4 b b r 5 b b r 6 b b r 7 t b r 0 t b r 1 t b r 2 t b r 3 t b r 4 t b r 5 t b r 6 t b r 7 r b r 0 r b r 1 r b r 2 r b r 3 r b r 4 r b r 5 r b r 6 l b r 0 l b r 1 l b r 2 l b r 3 l b r 4 l b r 5 l b r 6 d a 2 - l r e g i s t e r ( d a 2 l ) d a 2 - h r e g i s t e r ( d a 2 h ) ? ? ? ? ? ? 0 0 1 6 0 0 1 6 n 2 p a g e r e g i s t e r a r e a ( a d d r e s s e s 2 1 0 1 6 t o 2 1 f 1 6 , 2 4 0 1 6 t o 2 4 f 1 6 ) a d d r e s s r e g i s t e r b i t a l l o c a t i o ns t a t e i m m e d i a t e l y a f t e r r e s e t : f i x t o t h i s b i t t o 0 ( d o n o t w r i t e t o 1 ) : b i t a l l o c a t i o ns t a t e i m m e d i a t e l y a f t e r r e s e t f u n c t i o n b i t : n o f u n c t i o n b i t : f i x t o t h i s b i t t o 1 ( d o n o t w r i t e t o 0 ) n a m e : : 0 i m m e d i a t e l y a f t e r r e s e t : i n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t 0 1 ? : 1 i m m e d i a t e l y a f t e r r e s e t 1 0 0 0 0 0 r o m c o r r e c t i o n a d d r e s s 3 (h i g h- o r d e r ) r o m c o r r e c t i o n a d d r e s s 3 (l o w- o r d e r ) 0 0 1 6 0 0 1 6 r c r 2 18 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 fig. 8.2.6 internal state of processor status register and program counter at reset b 7 b 0 b 7 b 0 1 r e g i s t e r p r o c e s s o r s t a t u s r e g i s t e r ( p s ) b i t a l l o c a t i o ns t a t e i m m e d i a t e l y a f t e r r e s e t p r o g r a m c o u n t e r ( p c h ) p r o g r a m c o u n t e r ( p c l ) c o n t e n t s o f a d d r e s s f f f f 1 6 c o n t e n t s o f a d d r e s s f f f e 1 6 i z c d b t v n?? ? ? ? ? ? : f i x t o t h i s b i t t o 0 ( d o n o t w r i t e t o 1 ) : b i t a l l o c a t i o n s t a t e i m m e d i a t e l y a f t e r r e s e t f u n c t i o n b i t : n o f u n c t i o n b i t : f i x t o t h i s b i t t o 1 ( d o n o t w r i t e t o 0 ) n a m e : : 0 i m m e d i a t e l y a f t e r r e s e t : i n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t 0 1 ? : 1 i m m e d i a t e l y a f t e r r e s e t 1 0 19 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 8.3 interrupts interrupts can be caused by 16 different sources consisting of 3 ex- ternal, 14 internal, 1 software, and reset. interrupts are vectored in- terrupts with priorities as shown in table 8.3.1. reset is also included in the table because its operation is similar to an interrupt. when an interrupt is accepted, the contents of the program counter and processor status regis- ter are automatically stored into the stack. ? the interrupt disable flag i is set to 1 and the corresponding interrupt request bit is set to 0. ? the jump destination address stored in the vector address enters the program counter. other interrupts are disabled when the interrupt disable flag is set to 1. all interrupts except the brk instruction interrupt have an interrupt request bit and an interrupt enable bit. the interrupt request bits are in interrupt request registers 1 and 2 and the interrupt enable bits are in interrupt control registers 1 and 2. figures 8.3.2 to 8.3.6 show the interrupt-related registers. interrupts other than the brk instruction interrupt and reset are ac- cepted when the interrupt enable bit is 1, interrupt request bit is 1, and the interrupt disable flag is 0. the interrupt request bit can be set to 0 by a program, but not set to 1. the interrupt enable bit can be set to 0 and 1 by a program. reset is treated as a non-maskable interrupt with the highest priority. figure 8.3.1 shows interrupt control. 8.3.1 interrupt causes (1) v sync , osd, sprite osd interrupts the v sync interrupt is an interrupt request synchronized with the vertical sync signal. the osd interrupt occurs after character block display to the crt is completed. the sprite osd interrupt occurs at the completion of sprite display. (2) int1 to int3 external interrupts the int1 to int3 interrupts are external interrupt inputs, the sys- tem detects that the level of a pin changes from low to high or from high to low, and generates an interrupt request. the in- put active edge can be selected by bits 3 to 5 of the interrupt input polarity register (address 00cd 16 ) : when this bit is 0, a change from low to high is detected; when it is 1, a change from high to low is detected. note that both bits are cleared to 0 at reset. (3) timers 1 to 4 interrupts an interrupt is generated by an overflow of timers 1 to 4. vector addresses ffff 16 , fffe 16 fffd 16 , fffc 16 fffb 16 , fffa 16 fff9 16 , fff8 16 fff7 16 , fff6 16 fff5 16 , fff4 16 fff3 16 , fff2 16 fff1 16 , fff0 16 ffef 16 , ffee 16 ffed 16 , ffec 16 ffeb 16 , ffea 16 ffe9 16 , ffe8 16 ffe7 16 , ffe6 16 ffe5 16 , ffe4 16 ffe3 16 , ffe2 16 ffdf 16 , ffde 16 interrupt source reset osd interrupt int2 external interrupt int1 external interrupt sprite osd interrupt timer 4 interrupt f(x in )/4096 interrupt v sync interrupt timer 3 interrupt timer 2 interrupt timer 1 interrupt serial i/o interrupt multi-master i 2 c-bus interface interrupt int3 external interrupt a-d conversion interrupt brk instruction interrupt remarks non-maskable active edge selectable active edge selectable active edge selectable non-maskable table 8.3.1 interrupt vector addresses and priority 20 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 (4) serial i/o interrupt this is an interrupt request from the clock synchronous serial i/o function. (5) f(x in )/4096 interrupt the f (x in )/4096 interrupt occurs regularly with a f(x in )/4096 pe- riod. set bit 0 of the pwm mode register 1 to 0. (6) multi-master i 2 c-bus interface interrupt this is an interrupt request related to the multi-master i 2 c-bus interface. (7) a-d conversion interrupt the a-d conversion interrupt occurs at the completion of a-d conversion. (8) brk instruction interrupt this software interrupt has the least significant priority. it does not have a corresponding interrupt enable bit, and it is not af- fected by the interrupt disable flag i (non-maskable). fig. 8.3.1 interrupt control interrupt request bi t interrupt enable bit interrupt disable flag i brk instruction reset interrupt request 21 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 fig. 8.3.2 interrupt request register 1 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) [ a d d r e s s 0 0 f c bn a m e f u n c t i o n s a f t e r r e s e t rw i n t e r r u p t r e q u e s t r e g i s t e r 1 0 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d t i m e r 1 i n t e r r u p t r e q u e s t b i t ( t m 1 r ) 1 t i m e r 2 i n t e r r u p t r e q u e s t b i t ( t m 2 r ) 2 t i m e r 3 i n t e r r u p t r e q u e s t b i t ( t m 3 r ) 3t i m e r 4 i n t e r r u p t r e q u e s t b i t ( t m 4 r ) 4 o s d i n t e r r u p t r e q u e s t b i t ( o s d r ) 5 v s y n c i n t e r r u p t r e q u e s t b i t ( v s c r ) 6 m u l t i - m a s t e r i 2 c - b u s i n t e r f a c e i n t e r r u p t r e q u e s t b i t ( i i c r ) 7 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 0 ] 0 ] 0 ] 0 ] 0 ] 0 ] 0 ] ] : 0 c a n b e s e t b y s o f t w a r e , b u t 1 c a n n o t b e s e t . ] 1 6 ] r r r r r r r r i n t 3 e x t e r n a l i n t e r r u p t r e q u e s t b i t ( i t 3 r ) 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d fig. 8.3.3 interrupt request register 2 b 7b 6 b 5 b 4b 3 b 2 b 1 b 0 i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 ) [ a d d r e s s 0 0 f d bn a m e f u n c t i o n s a f t e r r e s e t rw i n t e r r u p t r e q u e s t r e g i s t e r 2 0 i n t 1 e x t e r n a l i n t e r r u p t r e q u e s t b i t ( i t 1 r ) 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 1 2 s e r i a l i / o i n t e r r u p t r e q u e s t b i t ( s 1 r ) 3 4 f ( x i n ) / 4 0 9 6 i n t e r r u p t r e q u e s t b i t ( m s r ) 5 7 f i x t h i s b i t t o 0 . 0 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 ] : 0 c a n b e s e t b y s o f t w a r e , b u t 1 c a n n o t b e s e t . 0 0 ] 0 0 ] 0 ] 0 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 1 6 ] r r r r ] r r r w s p r i t e o s d i n t e r r u p t r e q u e s t b i t ( s p r ) 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 6 a - d c o n v e r s i o n i n t e r r u p t r e q u e s t b i t ( a d r ) 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 ] r n o t h i n g i s a s s i g n e d . t h i s b i t i s a w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . i n t 2 e x t e r n a l i n t e r r u p t r e q u e s t b i t ( i t 2 r ) ] 22 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 fig. 8.3.4 interrupt control register 1 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) [ a d d r e s s 0 0 f e 1 6 ] bn a m ef u n c t i o n s rw i n t e r r u p t c o n t r o l r e g i s t e r 1 0 t i m e r 1 i n t e r r u p t e n a b l e b i t ( t m 1 e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 1 t i m e r 2 i n t e r r u p t e n a b l e b i t ( t m 2 e ) 2 t i m e r 3 i n t e r r u p t e n a b l e b i t ( t m 3 e ) 3 4 o s d i n t e r r u p t e n a b l e b i t ( o s d e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 0 0 0 0 0 rw rw rw rw rw r 7 t i m e r 4 i n t e r r u p t e n a b l e b i t ( t m 4 e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 5 v s y n c i n t e r r u p t e n a b l e b i t ( v s c e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 rw 6 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 rw a f t e r r e s e t i n t 3 e x t e r n a l i n t e r r u p t e n a b l e b i t ( i t 3 e ) m u l t i - m a s t e r i 2 c - b u s i n t e r f a c e i n t e r r u p t e n a b l e b i t ( i i c e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d w fig. 8.3.5 interrupt control register 2 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) [ a d d r e s s 0 0 f f 1 6 ] bn a m ef u n c t i o n s a f t e r r e s e t rw i n t e r r u p t c o n t r o l r e g i s t e r 2 0 i n t 1 e x t e r n a l i n t e r r u p t e n a b l e b i t ( i t 1 e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 1 i n t 2 e x t e r n a l i n t e r r u p t e n a b l e b i t ( i t 2 e ) 2 s e r i a l i / o i n t e r r u p t e n a b l e b i t ( s 1 e ) 3 4 f ( x i n ) / 4 0 9 6 i n t e r r u p t e n a b l e b i t ( m s e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 0 0 0 0 rw rw rw rw rw s p r i t e o s d i n t e r r u p t e n a b l e b i t ( s p e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 5 f i x t h i s b i t t o 0 . 0 r 6 a - d c o n v e r s i o n i n t e r r u p t e n a b l e b i t ( a d e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 rw 7 0 r n o t h i n g i s a s s i g n e d . t h i s b i t i s a w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . 0 w 23 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 fig. 8.3.6 interrupt input polarity register b 7b 6b 5b 4b 3b 2b 1b 0 i n t e r r u p t i n p u t p o l a r i t y r e g i s t e r ( i p ) [ a d d r e s s 0 0 c d 1 6 ] bn a m ef u n c t i o n a f t e r r e s e t r w i n t e r r u p t i n p u t p o l a r i t y r e g i s t e r 0 0 i n t 1 p o l a r i t y s w i t c h b i t ( p o l 1 ) 2 3 4 5 0 : p o s i t i v e p o l a r i t y 1 : n e g a t i v e p o l a r i t y 6 , 7 0r w 0r w 0r w i n t 2 p o l a r i t y s w i t c h b i t ( p o l 2 ) i n t 3 p o l a r i t y s w i t c h b i t ( p o l 3 ) f i x t h e s e b i t s t o 0 . 0w r 0w r 0 , 1 o s d c l o c k s e l e c t i o n b i t s ( o c g 0 , o c g 1 ) 0 r w s i n c e t h e m a i n c l o c k i s u s e d a s t h e c l o c k f o r o s d , t h e o s c i l l a t i o n f r e q u e n c y i s l i m i t e d . b e c a u s e o f t h i s , t h e c h a r a c t e r s i z e i n w i d t h ( h o r i z o n a l ) d i r e c t i o n i s a l s o l i m i t e d . i n t h i s c a s e , p i n s o s c 1 a n d o s c 2 a r e a l s o u s e d a s i n p u t p o r t s p 3 3 a n d p 3 4 r e s p e c t i v e l y . t h e c l o c k f o r o s d i s s u p p l i e d b y c o n n e c t i n g t h e f o l l o w i n g a c r o s s t h e p i n s o s c 1 a n d o s c 2 . h o w e v e r , i t i s n o t c o r r e s p o n d i n g t o t h e b i - s c a n m o d e . a c e r a m i c r e s o n a t o r o n l y f o r o s d a n d a f e e d b a c k r e s i s t o r a q u a r t z - c r y s t a l o s c i l l a t o r o n l y f o r o s d a n d a f e e d b a c k r e s i s t o r b 1 t h e c l o c k f o r o s d i s s u p p l i e d b y c o n n e c t i n g r c o r l c a c r o s s t h e p i n s o s c 1 a n d o s c 2 . h o w e v e r , i t i s n o t c o r r e s p o n d i n g t o t h e b i - s c a n m o d e . f u n c t i o n 00 b 0 o s d o s c i l l a t i o n f r e q u e n c y = f ( x i n ) 0 0 1 1 11 t h e c l o c k f o r o s d i s s u p p l i e d b y c o n n e c t i n g l c a c r o s s t h e p i n s o s c 1 a n d o s c 2 . i n t h e b i - s c a n m o d e , b e s u r e t o s e t t h i s . f i x t h i s b i t t o 0 . 0 : p o s i t i v e p o l a r i t y 1 : n e g a t i v e p o l a r i t y 0 : p o s i t i v e p o l a r i t y 1 : n e g a t i v e p o l a r i t y 0 24 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 8.4 timers this microcomputer has 4 timers: timers 1 to 4. all timers are 8-bit timers with the 8-bit timer latch. the timer block diagram is shown in figure 8.4.3. all of the timers count down and their divide ratio is 1/(n+1), where n is the value of timer latch. by writing a count value to the correspond- ing timer latch (addresses 00f0 16 to 00f3 16 : timers 1 to 4), the value is also set to a timer, simultaneously. the count value is decremented by 1. the timer interrupt request bit is set to 1 by a timer overflow at the next count pulse, after the count value reaches 00 16 . 8.4.1 timer 1 timer 1 can select one of the following count sources: ? f(x in )/16 ? f(x in )/4096 or f(x cin )/4096 the count source of timer 1 is selected by setting bit 0 of timer mode register 1 (address 00f4 16 ). timer 1 interrupt request occurs at timer 1 overflow. 8.4.2 timer 2 timer 2 can select one of the following count sources: ? f(x in )/16 ? timer 1 overflow signal ? external clock from the tim2 pin the count source of timer 2 is selected by setting bits 4 and 1 of timer mode register 1 (address 00f4 16 ). when timer 1 overflow sig- nal is a count source for the timer 2, the timer 1 functions as an 8-bit prescaler. timer 2 interrupt request occurs at timer 2 overflow. 8.4.3 timer 3 timer 3 can select one of the following count sources: ? f(x in )/16 ? external clock from the h sync pin ? external clock from the tim3 pin the count source of timer 3 is selected by setting bits 5 and 0 of timer mode register 2 (address 00f5 16 ). timer 3 interrupt request occurs at timer 3 overflow. 8.4.4 timer 4 timer 4 can select one of the following count sources: ? f(x in )/16 ? f(x in )/2 ? timer 3 overflow signal the count source of timer 3 is selected by setting bits 1 and 4 of timer mode register 2 (address 00f5 16 ). when timer 3 overflow sig- nal is a count source for the timer 4, the timer 3 functions as an 8-bit prescaler. timer 4 interrupt request occurs at timer 4 overflow. at reset, timers 3 and 4 are connected by hardware and ff 16 is automatically set in timer 3; 07 16 in timer 4. the f(x in )/16 is se- lected as the timer 3 count source. the internal reset is released by timer 4 overflow in this state and the internal clock is connected. at execution of the stp instruction, timers 3 and 4 are connected by hardware and ff 16 is automatically set in timer 3; 07 16 in timer 4. however, the f(x in )/16 is not selected as the timer 3 count source. so set both bit 0 of timer mode register 2 (address 00f5 16 ) and bit 6 at address 00c7 16 to 0 before execution of the stp instruction (f(x in )/16 is selected as the timer 3 count source). the internal stp state is released by timer 4 overflow in this state and the internal clock is connected. as a result of the above procedure, the program can start under a stable clock. however, when setting 1 to bit 5 of timer mode register 1 (address 00f4 16 ), timers 3 and 4 are not set the above value, the stp state is set by executing the stp instruction. this allows to program the time to return from the stp state. the timer-related registers is shown in figures 8.4.1 and 8.4.2. 25 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 fig. 8.4.2 timer mode register 2 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 t i m e r m o d e r e g i s t e r 2 ( t m 2 ) [ a d d r e s s 0 0 f 5 1 6 ] b a f t e r r e s e t rw t i m e r m o d e r e g i s t e r 2 0 n a m e f u n c t i o n s t i m e r 3 c o u n t s o u r c e s e l e c t i o n b i t ( t m 2 0 ) 0 rw 1 t i m e r 4 i n t e r n a l i n t e r r u p t c o u n t s o u r c e s e l e c t i o n b i t ( t m 2 1 ) 0 rw 2 3 t i m e r 3 c o u n t s t o p b i t ( t m 2 2 ) 0 : c o u n t s t a r t 1 : c o u n t s t o p t i m e r 4 c o u n t s t o p b i t ( t m 2 3 ) 0 : c o u n t s t a r t 1 : c o u n t s t o p 0 0 4 t i m e r 4 c o u n t s o u r c e s e l e c t i o n b i t ( t m 2 4 ) 0 : i n t e r n a l c l o c k s o u r c e 1 : f ( x i n ) / 2 0 5 t i m e r 3 e x t e r n a l c o u n t s o u r c e s e l e c t i o n b i t ( t m 2 5 ) 0 : t i m 3 p i n i n p u t 1 : h s y n c p i n i n p u t 0 rw rw rw rw 0 : f ( x i n ) / 1 6 1 : e x t e r n a l c l o c k s o u r c e 0 : t i m e r 3 o v e r f l o w s i g n a l 1 : f ( x i n ) / 1 6 6 , 7n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . 0 r fig. 8.4.1 timer mode register 1 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 t i m e r m o d e r e g i s t e r 1 ( t m 1 ) [ a d d r e s s 0 0 f 4 1 6 ] b a f t e r r e s e t w t i m e r m o d e r e g i s t e r 1 0 1 2 3 4 n a m e f u n c t i o n s t i m e r 1 c o u n t s o u r c e s e l e c t i o n b i t 1 ( t m 1 0 ) 0 : f ( x i n ) / 1 6 1 : f ( x i n ) / 4 0 9 6 t i m e r 2 c o u n t s o u r c e s e l e c t i o n b i t 1 ( t m 1 1 ) 0 : i n t e r r u p t c l o c k s o u r c e 1 : e x t e r n a l c l o c k f r o m t i m 2 p i n t i m e r 1 c o u n t s t o p b i t ( t m 1 2 ) 0 : c o u n t s t a r t 1 : c o u n t s t o p t i m e r 2 c o u n t s t o p b i t ( t m 1 3 ) 0 : c o u n t s t a r t 1 : c o u n t s t o p t i m e r 2 i n t e r n a l c o u n t s o u r c e s e l e c t i o n b i t 2 ( t m 1 4 ) r 0 0 0 0 0 w r w r w r w r w r 0 : f ( x i n ) / 1 6 1 : t i m e r 1 o v e r f l o w 5 < a t e x e c u t i o n o f s t p i n s t r u c t i o n > t i m e r s 3 a n d 4 a u t o s e t d i s a b l e b i t ( t m 1 5 ) 0 : a u t o s e t e n a b l e d 1 : a u t o s e t d i s a b l e d 0 w r 6 , 7n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . 0 r 26 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 fig. 8.4.3 timer block diagram t i m e r 1 ( 8 ) 1 / 4 0 9 6 1 / 2 1 / 8 t i m e r 1 l a t c h ( 8 ) 8 8 8 t m 1 0 t m 1 2 t m 1 4 t m 1 1 t m 1 3 t i m e r 2 ( 8 ) t i m e r 2 l a t c h ( 8 ) 8 8 8 t i m e r 3 ( 8 ) t i m e r 3 l a t c h ( 8 ) 8 8 8 t i m e r 4 ( 8 ) t i m e r 4 l a t c h ( 8 ) 8 8 8 d a t a b u s t i m e r 1 i n t e r r u p t r e q u e s t t i m e r 2 i n t e r r u p t r e q u e s t t m 2 0 t m 2 2 t m 2 5 t m 2 4 t m 2 3 t m 2 1 x i n t i m 2 t i m 3 s e l e c t i o n g a t e : c o n n e c t e d t o b l a c k s i d e a t r e s e t t m 1 : t i m e r m o d e r e g i s t e r 1 t m 2 : t i m e r m o d e r e g i s t e r 2 n o t e s1 : h i g h p u l s e w i d t h o f t i m e r e x t e r n a l c l o c k i n p u t s t i m 2 a n d t i m 3 n e e d s 4 m a c h i n e c y c l e s o r m o r e . 2 : w h e n t h e e x t e r n a l c l o c k s o u r c e i s s e l e c t e d , t i m e r s 1 , 2 , a n d 3 a r e c o u n t e d a t a r i s i n g e d g e o f i n p u t s i g n a l . 3 : i n t h e s t o p m o d e o r t h e w a i t m o d e , e x t e r n a l c l o c k i n p u t s t i m 2 a n d t i m 3 c a n n o t b e u s e d . f f 1 6 0 7 1 6 h s y n c r e s e t t i m e r 3 i n t e r r u p t r e q u e s t t i m e r 4 i n t e r r u p t r e q u e s t s t p i n s t r u c t i o n t m 1 5 27 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 8.5 serial i/o this microcomputer has a built-in serial i/o which can either transmit or receive 8-bit data serially in the clock synchronous mode. the serial i/o block diagram is shown in figure 8.5.1. the synchro- nous clock i/o pin (s clk ), and data output pin (s out ) also function as port p4, data input pin (s in ) also functions as port p2. bit 3 of the serial i/o mode register (address 00dc 16 ) selects whether the synchronous clock is supplied internally or externally (from the s clk pin). when an internal clock is selected, bits 1 and 0 select whether f(x in ) or f(x cin ) is divided by 4, 16, 32, or 64. to use s in pin for serial i/o, set the corresponding bit of the port p2 direction regis- ter (address 00c5 16 ) to 0. fig. 8.5.1 serial i/o block diagram the operation of the serial i/o is described below. the operation of the serial i/o differs depending on the clock source; external clock or internal clock. 8 s e r i a l i / o s h i f t r e g i s t e r ( 8 ) d a t a b u s s e r i a l i / o i n t e r r u p t r e q u e s t s y n c h r o n o u s c i r c u i t f r e q u e n c y d i v i d e r 1 / 3 2 1 / 41 / 6 4 s m 1 s m 0 s e r i a l i / o c o u n t e r ( 8 ) s m 5 : l s b m s b s s m 2 1 / 2 s m 6 x i n s i n s o u t s c l k 1 / 2 s m 3 p 2 1 l a t c h @ p 2 0 l a t c h s m 3 ( a d d r e s s 0 0 d d 1 6 ) ( s e e n o t e ) s m : s e r i a l i / o m o d e r e g i s t e r n o t e : w h e n t h e d a t a i s s e t i n t h e s e r i a l i / o r e g i s t e r ( a d d r e s s 0 0 d d 1 6 ) , t h e r e g i s t e r f u n c t i o n s a s t h e s e r i a l i / o s h i f t r e g i s t e r . s e l e c t i o n g a t e : c o n n e c t e d t o b l a c k s i d e a t r e s e t 1 / 1 6 28 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 internal clock : the serial i/o counter is set to 7 during the write cycle into the serial i/o register (address 00dd 16 ), and the transfer clock goes high forcibly. at each falling edge of the transfer clock after the write cycle, serial data is output from the s out pin. transfer direction can be selected by bit 5 of the serial i/o mode register. at each rising edge of the transfer clock, data is input from the s in pin and data in the serial i/o register is shifted 1 bit. after the transfer clock has counted 8 times, the serial i/o counter becomes 0 and the transfer clock stops at high. at this time the interrupt request bit is set to 1. fig. 8.5.2 serial i/o timing (for lsb first) synchronous cloc k transfer clock serial i/o register write signal serial i/o output s out d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 (note) serial i/o input s in note : when an internal clock is selected, the s out pin is at high-impedance after transfer is completed. interrupt request bit is set to ? external clock : the an external clock is selected as the clock source, the interrupt request is set to 1 after the transfer clock has been counted 8 counts. however, transfer operation does not stop, so the clock should be controlled externally. use the external clock of 1 mhz or less with a duty cycle of 50%. the serial i/o timing is shown in figure 8.5.2. when using an exter- nal clock for transfer, the external clock must be held at high for initializing the serial i/o counter. when switching between an inter- nal clock and an external clock, do not switch during transfer. also, be sure to initialize the serial i/o counter after switching. notes 1: on programming, note that the serial i/o counter is set by writing to the serial i/o register with the bit managing instructions, such as seb and clb. 2: when an external clock is used as the synchronous clock, write trans- mit data to the serial i/o register when the transfer clock input level is high. 29 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 fig. 8.5.3 serial i/o mode register b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 s e r i a l i / o m o d e r e g i s t e r ( s m ) [ a d d r e s s 0 0 d c 1 6 ] bn a m ef u n c t i o n s a f t e r r e s e t rw s e r i a l i / o m o d e r e g i s t e r 0 , 1i n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s ( s m 0 , s m 1 ) b 1 b 0 0 0 : f ( x i n ) / 4 0 1 : f ( x i n ) / 1 6 1 0 : f ( x i n ) / 3 2 1 1 : f ( x i n ) / 6 4 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t ( s m 2 ) 3 s e r i a l i / o p o r t s e l e c t i o n b i t ( s m 3 ) 6 5 t r a n s f e r d i r e c t i o n s e l e c t i o n b i t ( s m 5 ) 0 : p 2 0 , p 2 1 1 : s c l k , s o u t 0 : e x t e r n a l c l o c k 1 : i n t e r n a l c l o c k 0 : l s b f i r s t 1 : m s b f i r s t 0 0 0 0 0 0 rw rw rw r w rw rw 4 f i x t h i s b i t t o 0 . 7 n o t h i n g i s a s s i g n e d . t h i s b i t i s a w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . 0r s e r i a l i n p u t p i n s e l e c t i o n b i t ( s m 6 ) 0 : i n p u t s i g n a l f r o m s i n p i n . 1 : i n p u t s i g n a l f r o m s o u t p i n . 0 30 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 8.5.1 serial i/o common transmission/recep- tion mode by writing 1 to bit 6 of the serial i/o mode register, signals s in and s out are switched internally to be able to transmit or receive the serial data. figure 8.5.4 shows signals on serial i/o common transmission/re- ception mode. note: when receiving the serial data after writing ff 16 to the serial i/o regis- ter. fig. 8.5.4 signals on serial i/o common transmission/reception mode s e r i a l i / o s h i f t r e g i s t e r ( 8 ) 1 0 c l o c k s c l k s o u t s i n s m 6 s m : s e r i a l i / o m o d e r e g i s t e r 31 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 function in conformity with philips i 2 c-bus standard: 10-bit addressing format 7-bit addressing format high-speed clock mode standard clock mode in conformity with philips i 2 c-bus standard: master transmission master reception slave transmission slave reception 16.1 khz to 400 khz (at f = 4 mhz) table 8.6.1 multi-master i 2 c-bus interface functions item format communication mode scl clock frequency f : system clock = f(x in )/2 note : we are not responsible for any third partys infringement of patent rights or other rights attributable to the use of the control function (bits 6 and 7 of the i 2 c control register at address 00da 16 ) for connections between the i 2 c-bus interface and ports (scl1, scl2, sda1, sda2). 8.6 multi-master i 2 c-bus interface the multi-master i 2 c-bus interface is a serial communications cir- cuit, conforming to the philips i 2 c-bus data transfer format. this interface, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications. figure 8.6.1 shows a block diagram of the multi-master i 2 c-bus in- terface and table 8.6.1 shows multi-master i 2 c-bus interface func- tions. this multi-master i 2 c-bus interface consists of the i 2 c address reg- ister, the i 2 c data shift register, the i 2 c clock control register, the i 2 c control register, the i 2 c status register and other control circuits. fig. 8.6.1 block diagram of multi-master i 2 c-bus interface i 2 c address register (s0d) b7 b0 sad6 sad5 sad4 sad3 sad2 sad1 sad0 rbw noise elimination circuit serial data (sda) address comparator b7 i c data shift register b0 data control circuit i 2 c clock control register (s2) system clock ( f ) interrupt generating circuit interrupt request signal (iicirq) b7 mst trx bb pin al aas ad0 lrb b0 i c status register (s1) b7 b0 bsel1 bsel0 10bit sad als bc2 bc1 bc0 i 2 c control register (s1d) bit counter bb circuit clock control circuit noise elimination circuit serial clock (scl) b7 b0 ack ack bit fast mode ccr4 ccr3 ccr2 ccr1 ccr0 internal data bus clock division s0 al circuit eso 2 2 32 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 8.6.1 i 2 c data shift register the i 2 c data shift register (s0 : address 00d7 16 ) is an 8-bit shift register to store receive data and write transmit data. when transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the scl clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. when data is received, it is input to this register from bit 0 in synchronization with the scl clock, and each time one-bit data is input, the data of this register are shifted one bit to the left. the i 2 c data shift register is in a write enable status only when the eso bit of the i 2 c control register (address 00da 16 ) is 1. the bit counter is reset by a write instruction to the i 2 c data shift register. when both the eso bit and the mst bit of the i 2 c status register (address 00d9 16 ) are 1, the scl is output by a write instruction to the i 2 c data shift register. reading data from the i 2 c data shift regis- ter is always enabled regardless of the eso bit value. note: to write data into the i 2 c data shift register after setting the mst bit to 0 (slave mode), keep an interval of 8 machine cycles or more. fig. 8.6.2 data shift register b 7b 6b 5b 4b 3b 2b 1b 0 i 2 c d a t a s h i f t r e g i s t e r ( s 0 ) [ a d d r e s s 0 0 d 7 1 6 ] b f u n c t i o n sa f t e r r e s e trw i c d a t a s h i f t r e g i s t e r 0 t o 7 t h i s i s a n 8 - b i t s h i f t r e g i s t e r t o s t o r e r e c e i v e d a t a a n d w r i t e t r a n s m i t d a t a . i n d e t e r m i n a t e 2 n o t e : 2 t o w r i t e d a t a i n t o t h e i c d a t a s h i f t r e g i s t e r a f t e r s e t t i n g t h e m s t b i t t o 0 ( s l a v e m o d e ) , k e e p a n i n t e r v a l o f 8 m a c h i n e c y c l e s o r m o r e . n a m e d 0 t o d 7 rw 33 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 8.6.2 i 2 c address register the i 2 c address register (address 00d8 16 ) consists of a 7-bit slave address and a read/write bit. in the addressing mode, the slave ad- dress written in this register is compared with the address data to be received immediately after the start condition are detected. (1) bit 0: read/write bit (rbw) not used when comparing addresses, in the 7-bit addressing mode. in the 10-bit addressing mode, the first address data to be received is compared with the contents (sad6 to sad0 + rbw) of the i 2 c address register. the rbw bit is cleared to 0 automatically when the stop condition is detected. (2) bits 1 to 7: slave address (sad0Csad6) these bits store slave addresses. regardless of the 7-bit address- ing mode and the 10-bit addressing mode, the address data trans- mitted from the master is compared with the contents of these bits. fig. 8.6.3 i 2 c address register b 7b 6b 5b 4b 3b 2b 1b 0 0 r e a d / w r i t e b i t ( r b w ) 1 t o 7 s l a v e a d d r e s s ( s a d 0 t o s a d 6 ) < o n l y i n 1 0 - b i t a d d r e s s i n g ( i n s l a v e ) m o d e > t h e l a s t s i g n i f i c a n t b i t o f a d d r e s s d a t a i s c o m p a r e d . 0 : w a i t t h e f i r s t b y t e o f s l a v e a d d r e s s a f t e r s t a r t c o n d i t i o n ( r e a d s t a t e ) 1 : w a i t t h e f i r s t b y t e o f s l a v e a d d r e s s a f t e r r e s t a r t c o n d i t i o n ( w r i t e s t a t e ) 0 0 < i n b o t h m o d e s > t h e a d d r e s s d a t a i s c o m p a r e d . i 2 c a d d r e s s r e g i s t e r i 2 c a d d r e s s r e g i s t e r ( s 0 d ) [ a d d r e s s 0 0 d 8 1 6 ] b n a m e f u n c t i o n s a f t e r r e s e t r w r r w 34 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 8.6.3 i 2 c clock control register the i 2 c clock control register (address 00db 16 ) is used to set ack control, scl mode and scl frequency. (1) bits 0 to 4: scl frequency control bits (ccr0Cccr4) these bits control the scl frequency. (2) bit 5: scl mode specification bit (fast mode) this bit specifies the scl mode. when this bit is set to 0, the stan- dard clock mode is set. when the bit is set to 1, the high-speed clock mode is set. (3) bit 6: ack bit (ack bit) this bit sets the sda status when an ack clock ] is generated. when this bit is set to 0, the ack return mode is set and sda goes to low at the occurrence of an ack clock. when the bit is set to 1, the ack non-return mode is set. the sda is held in the high status at the occurrence of an ack clock. however, when the slave address matches the address data in the reception of address data at ack bit = 0, the sda is automatically made low (ack is returned). if there is a mismatch between the slave address and the address data, the sda is automatically made high (ack is not returned). ] ack clock: clock for acknowledgement fig. 8.6.4 i 2 c address register (4) bit 7: ack clock bit (ack) this bit specifies a mode of acknowledgment which is an acknowl- edgment response of data transmission. when this bit is set to 0, the no ack clock mode is set. in this case, no ack clock occurs after data transmission. when the bit is set to 1, the ack clock mode is set and the master generates an ack clock upon comple- tion of each 1-byte data transmission.the device for transmitting address data and control data releases the sda at the occurrence of an ack clock (make sda high) and receives the ack bit generated by the data receiving device. note: do not write data into the i 2 c clock control register during transmission. if data is written during transmission, the i 2 c clock generator is reset, so that data cannot be transmitted normally. b 7b 6b 5b 4b 3b 2b 1b 0 i 2 c c l o c k c o n t r o l r e g i s t e r ( s 2 ) [ a d d r e s s 0 0 d b 1 6 ] i 2 c c l o c k c o n t r o l r e g i s t e r 0 t o 4 s c l f r e q u e n c y c o n t r o l b i t s ( c c r 0 t o c c r 4 ) 7 5 6 s c l m o d e s p e c i f i c a t i o n b i t ( f a s t m o d e ) 0 : s t a n d a r d c l o c k m o d e 1 : h i g h - s p e e d c l o c k m o d e 0 s t a n d a r d c l o c k m o d e b n a m e f u n c t i o n s a f t e r r e s e t r w 0 0 0 a c k b i t ( a c k b i t ) a c k c l o c k b i t ( a c k ) 0 : a c k i s r e t u r n e d . 1 : a c k i s n o t r e t u r n e d . 0 : n o a c k c l o c k 1 : a c k c l o c k h i g h s p e e d c l o c k m o d e s e t u p d i s a b l e d s e t u p d i s a b l e d 0 0 t o 0 2 s e t u p d i s a b l e d 3 3 3 0 3 s e t u p d i s a b l e d 2 5 0 0 4 1 0 0 4 0 0 ( s e e n o t e ) 0 5 8 3 . 31 6 6 0 6 5 0 0 / c c r v a l u e 1 0 0 0 / c c r v a l u e . . . 1 7 . 2 3 4 . 5 1 d 1 6 . 63 3 . 3 1 e 1 6 . 1 3 2 . 3 1 f ( a t f = 4 m h z , u n i t : k h z ) n o t e : a t 4 0 0 k h z i n t h e h i g h - s p e e d c l o c k m o d e , t h e d u t y i s a s b e l o w . 0 p e r i o d : 1 p e r i o d = 3 : 2 i n t h e o t h e r c a s e s , t h e d u t y i s a s b e l o w . 0 p e r i o d : 1 p e r i o d = 1 : 1 s e t u p v a l u e o f c c r 4 C c c r 0 r w r w r w r w 35 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 8.6.4 i 2 c control register the i 2 c control register (address 00da 16 ) controls the data commu- nication format. (1) bits 0 to 2: bit counter (bc0Cbc2) these bits decide the number of bits for the next 1-byte data to be transmitted. an interrupt request signal occurs immediately after the number of bits specified with these bits are transmitted. when a start condition is received, these bits become 000 2 and the address data is always transmitted and received in 8 bits. (2) bit 3: i 2 c interface use enable bit (eso) this bit enables usage of the multimaster i 2 c bus interface. when this bit is set to 0, the use disable status is provided, so the sda and the scl become high-impedance. when the bit is set to 1, use of the interface is enabled. when eso = 0, the following is performed. ? pin = 1, bb = 0 and al = 0 are set (they are bits of the i 2 c status register at address 00d9 16 ). ? writing data to the i 2 c data shift register (address 00d7 16 ) is dis- abled. (3) bit 4: data format selection bit (als) this bit decides whether or not to recognize slave addresses. when this bit is set to 0, the addressing format is selected, so that ad- dress data is recognized. when a match is found between a slave address and address data as a result of comparison or when a gen- eral call (refer to 8.6.5 i 2 c status register, bit 1) is received, trans- mission processing can be performed. when this bit is set to 1, the free data format is selected, so that slave addresses are not recog- nized. (4) bit 5: addressing format selection bit (10bit sad) this bit selects a slave address specification format. when this bit is set to 0, the 7-bit addressing format is selected. in this case, only the high-order 7 bits (slave address) of the i 2 c address register (ad- dress 00d8 16 ) are compared with address data. when this bit is set to 1, the 10-bit addressing format is selected, all the bits of the i 2 c address register are compared with address data. (5) bits 6 and 7: connection control bits between i 2 c-bus interface and ports (bsel0, bsel1) these bits controls the connection between scl and ports or sda and ports (refer to figure 8.6.5). fig. 8.6.5 connection port control by bsel0 and bsel1 0 1 b s e l 0 p 1 1 /s c l 1 p 1 2 / s c l 2 0 1 b s e l 1 0 1 b s e l 0 p 1 3 / s d a 1 p 1 4 / s d a 2 0 1 b s e l 1 m u l t i - m a s t e r i 2 c - b u s i n t e r f a c e s c l s d a 36 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 fig. 8.6.6 i 2 c control register b 7b 6b 5b 4b 3b 2b 1b 0 0 t o 2 b i t c o u n t e r ( n u m b e r o f t r a n s m i t / r e c i e v e b i t s ) ( b c 0 t o b c 2 ) b 2 b 1 b 0 0 0 0 : 8 0 0 1 : 7 0 1 0 : 6 0 1 1 : 5 1 0 0 : 4 1 0 1 : 3 1 1 0 : 2 1 1 1 : 1 3 i 2 c - b u s i n t e r f a c e u s e e n a b l e b i t ( e s o ) 0 : d i s a b l e d 1 : e n a b l e d 4d a t a f o r m a t s e l e c t i o n b i t ( a l s ) 0 : a d d r e s s i n g f o r m a t 1 : f r e e d a t a f o r m a t 5a d d r e s s i n g f o r m a t s e l e c t i o n b i t ( 1 0 b i t s a d ) 0 : 7 - b i t a d d r e s s i n g f o r m a t 1 : 1 0 - b i t a d d r e s s i n g f o r m a t 6 , 7 c o n n e c t i o n c o n t r o l b i t s b e t w e e n i c - b u s i n t e r f a c e a n d p o r t s ( b s e l 0 , b s e l 1 ) b 7 b 6 c o n n e c t i o n p o r t ( s e e n o t e ) 0 0 : n o n e 0 1 : s c l 1 , s d a 1 1 0 : s c l 2 , s d a 2 1 1 : s c l 1 , s d a 1 , s c l 2 , s d a 2 0 0 0 0 0 i 2 c c o n t r o l r e g i s t e r ( s 1 d ) [ a d d r e s s 0 0 d a 1 6 ] i 2 c c o n t r o l r e g i s t e r b n a m e f u n c t i o n s a f t e r r e s e t r w 2 r w r w r w r w r w n o t e : w h e n u s i n g p o r t s p 1 1 - p 1 4 a s i 2 c - b u s i n t e r f a c e , t h e o u t p u t s t r u c t u r e c h a n g e s a u t o m a t i c a l l y f r o m c m o s o u t p u t t o n - c h a n n e l o p e n - d r a i n o u t p u t . 37 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 8.6.5 i 2 c status register the i 2 c status register (address 00d9 16 ) controls the i 2 c-bus inter- face status. the low-order 4 bits are read-only bits and the high- order 4 bits can be read out and written to. (1) bit 0: last receive bit (lrb) this bit stores the last bit value of received data and can also be used for ack receive confirmation. if ack is returned when an ack clock occurs, the lrb bit is set to 0. if ack is not returned, this bit is set to 1. except in the ack mode, the last bit value of received data is input. the state of this bit is changed from 1 to 0 by executing a write instruction to the i 2 c data shift register (address 00d7 16 ). (2) bit 1: general call detecting flag (ad0) this bit is set to 1 when a general call ] whose address data is all 0 is received in the slave mode. by a general call of the master device, every slave device receives control data after the general call. the ad0 bit is set to 0 by detecting the stop condition or start condition. ] general call: the master transmits the general call address 00 16 to all slaves. (3) bit 2: slave address comparison flag (aas) this flag indicates a comparison result of address data. n in the slave receive mode, when the 7-bit addressing format is selected, this bit is set to 1 in one of the following conditions. ? the address data immediately after occurrence of a start con- dition matches the slave address stored in the high-order 7 bits of the i 2 c address register (address 00d8 16 ). ? a general call is received. n in the slave reception mode, when the 10-bit addressing format is selected, this bit is set to 1 with the following condition. ? when the address data is compared with the i 2 c address regis- ter (8 bits consists of slave address and rbw), the first bytes match. n the state of this bit is changed from 1 to 0 by executing a write instruction to the i 2 c data shift register (address 00d7 16 ). (4) bit 3: arbitration lost ] detecting flag (al) n the master transmission mode, when a device other than the mi- crocomputer sets the sda to l,, arbitration is judged to have been lost, so that this bit is set to 1. at the same time, the trx bit is set to 0, so that immediately after transmission of the byte whose arbitra- tion was lost is completed, the mst bit is set to 0. when arbitration is lost during slave address transmission, the trx bit is set to 0 and the reception mode is set. consequently, it becomes possible to re- ceive and recognize its own slave address transmitted by another master device. ] arbitration lost: the status in which communication as a master is disabled. (5) bit 4: i 2 c-bus interface interrupt request bit (pin) this bit generates an interrupt request signal. each time 1-byte data is transmitted, the state of the pin bit changes from 1 to 0. at the same time, an interrupt request signal is sent to the cpu. the pin bit is set to 0 in synchronization with a falling edge of the last clock (including the ack clock) of an internal clock and an interrupt re- quest signal occurs in synchronization with a falling edge of the pin bit. when the pin bit is 0, the scl is kept in the 0 state and clock generation is disabled. figure 8.6.8 shows an interrupt request sig- nal generating timing chart. the pin bit is set to 1 in any one of the following conditions. ? executing a write instruction to the i 2 c data shift register (address 00d7 16 ). ? when the eso bit is 0 ? at reset the conditions in which the pin bit is set to 0 are shown below: ? immediately after completion of 1-byte data transmission (includ- ing when arbitration lost is detected) ? immediately after completion of 1-byte data reception ? in the slave reception mode, with als = 0 and immediately after completion of slave address or general call address reception ? in the slave reception mode, with als = 1 and immediately after completion of address data reception (6) bit 5: bus busy flag (bb) this bit indicates the status of use of the bus system. when this bit is set to 0, this bus system is not busy and a start condition can be generated. when this bit is set to 1, this bus system is busy and the occurrence of a start condition is disabled by the start condition duplication prevention function (see note). this flag can be written by software only in the master transmission mode. in the other modes, this bit is set to 1 by detecting a start condition and set to 0 by detecting a stop condition. when the eso bit of the i 2 c control register (address 00da 16 ) is 0 and at reset, the bb flag is kept in the 0 state. (7) bit 6: communication mode specification bit (transfer direction specification bit: trx) this bit decides the direction of transfer for data communication. when this bit is 0, the reception mode is selected and the data of a trans- mitting device is received. when the bit is 1, the transmission mode is selected and address data and control data are output into the sda in synchronization with the clock generated on the scl. when the als bit of the i 2 c control register (address 00da 16 ) is 0 in the slave reception mode is selected, the trx bit is set to 1 ___ (transmit) if the least significant bit (r/w bit) of the address data trans- ___ mitted by the master is 1. when the als bit is 0 and the r/w bit is 0, the trx bit is cleared to 0 (receive). the trx bit is cleared to 0 in one of the following conditions. ? when arbitration lost is detected. ? when a stop condition is detected. ? when occurence of a start condition is disabled by the start condition duplication prevention function (note). ? with mst = 0 and when a start condition is detected. ? with mst = 0 and when ack non-return is detected. ? at reset 38 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 (8) bit 7: communication mode specification bit (master/slave specification bit: mst) this bit is used for master/slave specification for data communica- tion. when this bit is 0, the slave is specified, so that a start condition and a stop condition generated by the master are received, and data communication is performed in synchronization with the clock generated by the master. when this bit is 1, the master is specified and a start condition and a stop condition are gener- ated, and also the clocks required for data communication are gen- erated on the scl. the mst bit is cleared to 0 in one of the following conditions. ? immediately after completion of 1-byte data transmission when arbitration lost is detected ? when a stop condition is detected. ? when occurence of a start condition is disabled by the start condition duplication preventing function (note). ? at reset fig. 8.6.7 i 2 c status register b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 i 2 c s t a t u s r e g i s t e r ( s 1 ) [ a d d r e s s 0 0 d 9 1 6 ] i 2 c s t a t u s r e g i s t e r 0 3 4 5 6 , 7 b 7 b 6 0 0 : s l a v e r e c i e v e m o d e 0 1 : s l a v e t r a n s m i t m o d e 1 0 : m a s t e r r e c i e v e m o d e 1 1 : m a s t e r t r a n s m i t m o d e 1 2 0 0 0 1 0 b n a m e f u n c t i o n s a f t e r r e s e t r w c o m m u n i c a t i o n m o d e s p e c i f i c a t i o n b i t s ( t r x , m s t ) 0 : b u s f r e e 1 : b u s b u s y b u s b u s y f l a g ( b b ) 0 : i n t e r r u p t r e q u e s t i s s u e d 1 : n o i n t e r r u p t r e q u e s t i s s u e d i 2 c - b u s i n t e r f a c e i n t e r r u p t r e q u e s t b i t ( p i n ) 0 : n o t d e t e c t e d 1 : d e t e c t e d a r b i t r a t i o n l o s t d e t e c t i n g f l a g ( a l ) ( s e e n o t e ) 0 : a d d r e s s m i s m a t c h 1 : a d d r e s s m a t c h s l a v e a d d r e s s c o m p a r i s o n f l a g ( a a s ) ( s e e n o t e ) 0 : n o g e n e r a l c a l l d e t e c t e d 1 : g e n e r a l c a l l d e t e c t e d g e n e r a l c a l l d e t e c t i n g f l a g ( a d 0 ) ( s e e n o t e ) 0 : l a s t b i t = 0 1 : l a s t b i t = 1 l a s t r e c e i v e b i t ( l r b ) ( s e e n o t e ) n o t e : t h e s e b i t s a n d f l a g s c a n b e r e a d o u t , b u t c a n n n o t b e w r i t t e n . i n d e t e r m i n a t e r r r r r w r w 0 r w ( s e e n o t e ) ( s e e n o t e ) ( s e e n o t e ) ( s e e n o t e ) fig. 8.6.8 interrupt request signal generation timing sc l pin iicir q note: the start condition duplication prevention function disables the start condition generation, reset of bit counter reset, and scl output, when the following condition is satisfied: a start condition is set by another master device. 39 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 8.6.6 start condition generation method when the eso bit of the i 2 c control register (address 00da 16 ) is 1, execute a write instruction to the i 2 c status register (address 00d9 16 ) to set the mst, trx and bb bits to 1. a start condition will then be generated. after that, the bit counter becomes 000 2 and an scl for 1 byte is output. the start condition generation timing and bb bit set timing are different in the standard clock mode and the high- speed clock mode. refer to figure 8.6.9 for the start condition generation timing diagram, and table 8.6.2 for the start condition/ stop condition generation timing table. fig. 8.6.9 start condition generation timing diagram i 2 c status register write signal set time for bb flag hold time setup time scl sda bb flag setup time 8.6.7 stop condition generation method when the eso bit of the i 2 c control register (address 00da 16 ) is 1, execute a write instruction to the i 2 c status register (address 00d9 16 ) for setting the mst bit and the trx bit to 1 and the bb bit to 0. a stop condition will then be generated. the stop condition genera- tion timing and the bb flag reset timing are different in the standard clock mode and the high-speed clock mode. refer to figure 8.6.10 for the stop condition generation timing diagram, and table 8.6.2 for the start condition/stop condition generation timing table. fig. 8.6.10 stop condition generation timing diagram table 8.6.2 start condition/stop condition generation tim- ing table item setup time (start condition) setup time (stop condition) hold time set/reset time for bb flag standard clock mode 5.0 m s (20 cycles) 4.25 m s (17 cycles) 5.0 m s (20 cycles) 3.0 m s (12 cycles) high-speed clock mode 2.5 m s (10 cycles) 1.75 m s (7 cycles) 2.5 m s (10 cycles) 1.5 m s (6 cycles) note: absolute time at f = 4 mhz. the value in parentheses denotes the number of f cycles. i 2 c status register write signal reset time for bb flag hold time setup time scl sda bb flag 40 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 8.6.8 start/stop condition detect conditions the start/stop condition detect conditions are shown in figure 8.6.11 and table 8.6.3. only when the 3 conditions of table 8.6.3 are satisfied, a start/stop condition can be detected. note: when a stop condition is detected in the slave mode (mst = 0), an interrupt request signal iicirq is generated to the cpu. fig. 8.6.11 start condition/stop condition detect timing dia- gram standard clock mode 6.5 m s (26 cycles) < scl release time 3.25 m s (13 cycles) < setup time 3.25 m s (13 cycles) < hold time high-speed clock mode 1.0 m s (4 cycles) < scl release time 0.5 m s (2 cycles) < setup time 0.5 m s (2 cycles) < hold time table 8.6.3 start condition/stop condition detect conditions note: absolute time at f = 4 mhz. the value in parentheses denotes the num- ber of f cycles. hold time setup time scl sda (start condition) sda (stop condition) scl release time hold time setup time 8.6.9 address data communication there are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. the respective ad- dress communication formats is described below. (1) 7-bit addressing format to meet the 7-bit addressing format, set the 10bit sad bit of the i 2 c control register (address 00da 16 ) to 0. the first 7-bit address data transmitted from the master is compared with the high-order 7-bit slave address stored in the i 2 c address register (address 00d8 16 ). at the time of this comparison, address comparison of the rbw bit of the i 2 c address register (address 00d8 16 ) is not made. for the data transmission format when the 7-bit addressing format is selected, refer to figure 8.6.12, (1) and (2). (2) 10-bit addressing format to meet the 10-bit addressing format, set the 10bit sad bit of the i 2 c control register (address 00da 16 ) to 1. an address comparison is made between the first-byte address data transmitted from the master and the 7-bit slave address stored in the i 2 c address register (address 00d8 16 ). at the time of this comparison, an address com- parison between the rbw bit of the i 2 c address register (address 00d8 16 ) and the r/w bit which is the last bit of the address data transmitted from the master is made. in the 10-bit addressing mode, the r/w bit which is the last bit of the address data not only specifies the direction of communication for control data but also is processed as an address data bit. when the first-byte address data matches the slave address, the aas bit of the i 2 c status register (address 00d9 16 ) is set to 1. after the second-byte address data is stored into the i 2 c data shift register (address 00d7 16 ), make an address comparison between the sec- ond-byte data and the slave address by software. when the address data of the 2nd bytes matches the slave address, set the rbw bit of the i 2 c address register (address 00d8 16 ) to 1 by software. this processing can match the 7-bit slave address and r/w data, which are received after a restart condition is detected, with the value of the i 2 c address register (address 00d8 16 ). for the data transmis- sion format when the 10-bit addressing format is selected, refer to figure 8.6.12, (3) and (4). 41 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 8.6.10 example of master transmission an example of master transmission in the standard clock mode, at the scl frequency of 100 khz and in the ack return mode is shown below. set a slave address in the high-order 7 bits of the i 2 c address register (address 00d8 16 ) and 0 in the rbw bit. set the ack return mode and scl = 100 khz by setting 85 16 in the i 2 c clock control register (address 00db 16 ). a set 10 16 in the i 2 c status register (address 00d9 16 ) and hold the scl at the high. ? set a communication enable status by setting 48 16 in the i 2 c control register (address 00da 16 ). ? set the address data of the destination of transmission in the high- order 7 bits of the i 2 c data shift register (address 00d7 16 ) and set 0 in the least significant bit. ? set f0 16 in the i 2 c status register (address 00d9 16 ) to generate a start condition. at this time, an scl for 1 byte and an ack clock automatically occurs. ? set transmit data in the i 2 c data shift register (address 00d7 16 ). at this time, an scl and an ack clock automatically occurs. ? when transmitting control data of more than 1 byte, repeat step ? . set d0 16 in the i 2 c status register (address 00d9 16 ). after this, if ack is not returned or transmission ends, a stop condition will be generated. 8.6.11 example of slave reception an example of slave reception in the high-speed clock mode, at the scl frequency of 400 khz, in the ack non-return mode, using the addressing format, is shown below. set a slave address in the high-order 7 bits of the i 2 c address register (address 00d8 16 ) and 0 in the rbw bit. set the no ack clock mode and scl = 400 khz by setting 25 16 in the i 2 c clock control register (address 00db 16 ). a set 10 16 in the i 2 c status register (address 00d9 16 ) and hold the scl at the high. ? set a communication enable status by setting 48 16 in the i 2 c control register (address 00da 16 ). ? when a start condition is received, an address comparison is made. ? ?when all transmitted address are0 (general call): ad0 of the i 2 c status register (address 00d9 16 ) is set to 1and an interrupt request signal occurs. ?when the transmitted addresses match the address set in : ass of the i 2 c status register (address 00d9 16 ) is set to 1 and an interrupt request signal occurs. ?in the cases other than the above: ad0 and aas of the i 2 c status register (address 00d9 16 ) are set to 0 and no interrupt request signal occurs. ? set dummy data in the i 2 c data shift register (address 00d7 16 ). ? when receiving control data of more than 1 byte, repeat step ? . when a stop condition is detected, the communication ends. 42 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 fig. 8.6.12 address data communication format s slave address a data a data a/a p r/w 7 bits ? 1 to 8 bits 1 to 8 bit s s slave address a data a data ap 7 bits ? 1 to 8 bits 1 to 8 bit s (1) a master-transmitter transmits data to a slave-receiver s slave address 1st 7 bits a a data 7 bits ? 8 bits 1 to 8 bits (2) a master-receiver receives data from a slave-transmitte r slave address 2nd byte a data a/a p 1 to 8 bits s slave address 1st 7 bits a a 7 bits ? 8 bits 7 bit s (3) a master-transmitter transmits data to a slave-receiver with a 10-bit address slave address 2nd byte data 1 to 8 bits sr slave address 1st 7 bits a data a p 1 to 8 bits ? (4) a master-receiver receives data from a slave-transmitter with a 10-bit address s : start condition p : stop condition a : ack bit r/w : read/write bit sr : restart condition from master to slave from slave to master r/w r/w r/w r/w 8.6.12 precautions when using multi-master i 2 c-bus interface (1) read-modify-write instruction the precautions when the raead-modify-write instruction such as seb, clb etc. is executed for each register of the multi-master i 2 c-bus interface are described below. ?i 2 c data shift register (s0) when executing the read-modify-write instruction for this register during transfer, data may become a value not intended. ?i 2 c address register (s0d) when the read-modify-write instruction is executed for this register at detecting the stop condition, data may become a value not ______ intended. it is because hardware changes the read/write bit (rbw) at the above timing. ?i 2 c status register (s1) do not execute the read-modify-write instruction for this register because all bits of this register are changed by hardware. ?i 2 c control register (s1d) when the read-modify-write instruction is executed for this register at detecting the start condition or at completing the byte transfer, data may become a value not intended. because hardware changes the bit counter (bc0Cbc2) at the above timing. ?i 2 c clock control register (s2) the read-modify-write instruction can be executed for this register. (2) start condition generating procedure us- ing multi-master procedure example (the necessary conditions of the generating procedure are described as the following to ? ). ? ? lda (taking out of slave address value) sei (interrupt disabled) bbs 5,s1,busbusy (bb flag confirming and branch process) busfree: sta s0 (writing of slave address value) ldm #$f0, s1 (trigger of start condition generating) cli (interrupt enabled) ? ? busbusy: cli (interrupt enabled) ? ? use sta, stx or sty of the zero page addressing instruction for writing the slave address value to the i 2 c data shift register. a use ldm instruction for setting trigger of start condition gener- ating. ? write the slave address value of above and set trigger of start condition generating of above a continuously shown the above procedure example. ? disable interrupts during the following three process steps: ? bb flag confirming ? writing of slave address value ? trigger of start condition generating when the condition of the bb flag is bus busy, enable interrupts immediately. 43 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 (3) restart condition generating procedure procedure example (the necessary conditions of the generating procedure are described as the following to ? .) execute the following procedure when the pin bit is 0. ? ? ldm #$00, s1 (select slave receive mode) lda (taking out of slave address value) sei (interrupt disabled) sta s0 (writing of slave address value) ldm #$f0, s1 (trigger of restart condition generating) cli (interrupt enabled) ? ? select the slave receive mode when the pin bit is 0. do not write 1 to the pin bit. neither 0 nor 1 is specified for the writing to the bb bit. the trx bit becomes 0 and the sda pin is released. a the scl pin is released by writing the slave address value to the i 2 c data shift register. use sta, stx or sty of the zero page addressing instruction for writing. ? use ldm instruction for setting trigger of restart condition gen- erating. ? write the slave address value of above a and set trigger of re- start condition generating of above ? continuously shown the above procedure example. ? disable interrupts during the following two process steps: ? writing of slave address value ? trigger of restart condition generating (4) stop condition generating procedure procedure example (the necessary conditions of the generating procedure are described as the following to ? .) ? ? sei (interrupt disabled) ldm #$c0, s1 (select master transmit mode) nop (set nop) ldm #$d0, s1 (trigger of stop condition generating) cli (interrupt enabled) ? ? write 0 to the pin bit when master transmit mode is select. a execute nop instruction after setting of master transmit mode. also, set trigger of stop condition generating within 10 cycles af- ter selecting of master trasmit mode. ? disable interrupts during the following two process steps: ? select of master transmit mode ? trigger of stop condition generating (5) writing to i 2 c status register do not execute an instruction to set the pin bit to 1 from 0 and an instruction to set the mst and trx bits to 0 from 1 simultaneously. it is because it may enter the state that the scl pin is released and the sda pin is released after about one machine cycle. do not ex- ecute an instruction to set the mst and trx bits to 0 from 1 si- multaneously when the pin bit is 1. it is because it may become the same as above. (6) process of after stop condition generating do not write data in the i 2 c data shift register s0 and the i 2 c status register s1 until the bus busy flag bb becomes 0 after generating the stop condition in the master mode. it is because the stop condition waveform might not be normally generated. reading to the above registers do not have the problem. 44 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 8.7 pwm output function this microcomputer is equipped with two 14-bit pwms (da1, da2) and six 8-bit pwms (pwm0Cpwm5). da1 and da2 have a 14-bit resolution with the minimum resolution bit width of 0.25 m s and a repeat period of 4096 m s (for f(x in ) = 8 mhz). pwm0Cpwm5 have the same circuit structure and an 8-bit resolution with minimum reso- lution bit width of 4 m s and repeat period of 1024 m s (for f(x in ) = 8 mhz). figure 8.7.1 shows the pwm block diagram. the pwm timing gen- erating circuit applies individual control signals to da1, da2 and pwm0Cpwm5 using f(x in ) divided by 2 as a reference signal. 8.7.1 data setting when outputting da1, first set the high-order 8 bits to the da1-h register (address 00ce 16 ), then the low-order 6 bits to the da1-l register (address 00cf 16 ). when outputting da1, first set the high- order 8 bits to the da2-h register (address 024e 16 ), then the low- order 6 bits to the da2-l register (address 024f 16 ). when outputting pwm0Cpwm5, set 8-bit output data to the pwmi register (i means 0 to 5; addresses 00d0 16 to 00d4 16 , 00f6 16 ). 8.7.2 transferring data from registers to pwm circuit data transfer from the 8-bit pwm register to the 8-bit pwm circuit is executed at writing data to the register. the signal output from the 8-bit pwm output pin corresponds to the contents of this register. also, data transfer from the da1 register (addresses 00ce 16 and 00cf 16 ) to the 14-bit pwm circuit is executed at writing data to the da1-l register (address 00cf 16 ). reading from the da1-h register (address 00ce 16 ) means reading this transferred data. data trans- fer from the da2 register (addresses 024e 16 and 024f 16 ) to the 14- bit pwm circuit is executed at writing data to the da2-l register (ad- dress 024f 16 ). reading from the da2-h register (address 024e 16 ) means reading this transferred data. accordingly, it is possible to confirm the data being output from the dai (i = 1, 2) output pin by reading the dai (i = 1, 2) register. 8.7.3 operating of 8-bit pwm the following explains pwm operation. first, set the bit 0 of pwm output control register 1 (address 00d5 16 ) to 0 (at reset, bit 0 is already set to 0 automatically), so that the pwm count source is supplied. pwm0Cpwm5 are also used as pins p0 0 Cp0 5 , respectively. for pwm0Cpwm5, set the corresponding bits of the ports p0 direction register to 1 (output mode). and select each output polarity by bit 3 of pwm output control register 2 (address 00d6 16 ). then, set bits 2 to 7 of pwm output control register 1 to 1 (pwm output). the pwm waveform is output from the pwm output pins by setting these registers. figure 8.7.2 shows the 8-bit pwm timing. one cycle (t) is com- posed of 256 (2 8 ) segments. the 8 kinds of pulses, relative to the weight of each bit (bits 0 to 7), are output inside the circuit during 1 cycle. refer to figure 8.7.2 (a). the 8-bit pwm outputs waveform which is the logical sum (or) of pulses corresponding to the con- tents of bits 0 to 7 of the 8-bit pwm register. several examples are shown in figure 8.7.2 (b). 256 kinds of output (high area: 0/256 to 255/256) are selected by changing the contents of the pwm register. a length of entirely high output cannot be output, i.e. 256/256. 8.7.4 operating of 14-bit pwm for da1, as with 8-bit pwm, set the bit 0 of pwm output control register 1 (address 00d5 16 ) to 0 (at reset, bit 0 is already set to 0 automatically), so that the pwm count source is supplied. next, se- lect the output polarity by bit 2 of pwm output control register 2 (ad- dress 00d6 16 ). then, the 14-bit pwm outputs from the da1 output pin by setting bit 1 of pwm output control register 1 to 0 (at reset, this bit already set to 0 automatically) to select the da1 output. for da2 as with da1, set the bit 0 of pwm output control register 1 (address 00d5 16 ) to 0 (at reset, bit 0 is already set to 0 automati- cally), so that pwm count source is supplied. next, select the output polarity by bit 4 of pwm output control register 2 (address 00d6 16 ). then, the 14-bit pwm outputs from the da2 output pin by setting bit 5 of pwm output control register 1 to 0 (at reset, this bit already set to 0 automatically) to select the da2 output. the output example of the 14-bit pwm is shown in figure 8.7.3. the 14-bit pwm divides the data of the dai latch (i = 1, 2) into the low-order 6 bits and the high-order 8 bits. the fundamental waveform is determined with the high-order 8-bit data d h . a high area with a length t 5 d h (high area of funda- mental waveform) is output every short area of t = 256 t = 64 m s ( t is the minimum resolution bit width of 250 ns). the high level area increase interval (t m ) is determined with the low-order 6-bit data d l . the high are of smaller intervals t m shown in table 5 is longer by t than that of other smaller intervals in pwm repeat period t = 64t. thus, a rectangular waveform with the different high width is output from the dai pins (i = 1, 2). accordingly, the pwm output changes by t unit pulse width by changing the contents of the dai-h and dai-l registers (i = 1, 2). a length of entirely high cannot be output, i. e. 256/256. 8.7.5 output after reset at reset, the output of ports p0 0 Cp0 5 and p1 7 are in the high-imped- ance state, and the contents of the pwm register and the pwm circuit are undefined. note that after reset, the pwm output is unde- fined until setting the pwm register. lsb table 8.7.1 relation between the low-order 6-bit data and high- level area increase interval area longer by t than that of other t m (m = 0 to 63) nothing m = 32 m = 16, 48 m = 8, 24, 40, 56 m = 4, 12, 20, 28, 36, 44, 52, 60 m = 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62 m = 1, 3, 5, 7, ................................. 57, 59, 61, 63 low-order 6 bits of data 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 45 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 fig. 8.7.1 pwm block diagram p w m 1 r e g i s t e r ( a d d r e s s 0 0 d 1 1 6 ) 1 / 2 x i n p w m t i m i n g g e n e r a t i n g c i r c u i t p w m r e g i s t e r ( a d d r e s s 0 0 d 0 1 6 ) b 7b 0 8 8 - b i t p w m c i r c u i t p n 3 p 0 0 p w 2 d 0 0 p w m 0 p 0 1 p w 3 d 0 1 p w m 1 p 0 2 p w 4 d 0 2 p w m 2 p 0 3 p w 5 d 0 3 p w m 3 p 0 4 p w 6 d 0 4 p w m 4 p 0 5 p w 7 d 0 5 p w m 5 p w m 2 r e g i s t e r ( a d d r e s s 0 0 d 2 1 6 ) p w m 3 r e g i s t e r ( a d d r e s s 0 0 d 3 1 6 ) p w m 4 r e g i s t e r ( a d d r e s s 0 0 d 4 1 6 ) p w m 5 r e g i s t e r ( a d d r e s s 0 0 f 6 1 6 ) d a t a b u s i n s i d e o f i s a s s a m e c o n t e n t s w i t h t h e o t h e r s . s e l e c t i o n g a t e : c o n n e c t e d t o b l a c k s i d e a t r e s e t . p a s s g a t e p w: p w m m o d e r e g i s t e r 1 [ a d d r e s s 0 0 d 5 1 6 ] p n: p w m m o d e r e g i s t e r 2 [ a d d r e s s 0 0 d 6 1 6 ] d 0: p o r t p 0 d i r e c t i o n r e g i s t e r [ a d d r e s s 0 0 c 1 1 6 ] p 0: p o r t p 0 r e g i s t e r [ a d d r e s s 0 0 c 0 1 6 ] p 1: p o r t p 1 r e g i s t e r [ a d d r e s s 0 0 c 2 1 6 ] p 3: p o r t p 3 r e g i s t e r [ a d d r e s s 0 0 c 4 1 6 ] p w 0 1 4- b i t p w m c i r c u i t p n 4 p 1 7 p w 1 m s b d a 2 - h r e g i s t e r ( a d d r e s s 0 2 4 e 1 6 ) d a 2 l a t c h ( 1 4 b i t s) d a 2 - l r e g i s t e r ( s e e n o t e ) ( a d d r e s s 0 2 4 f 1 6 ) l s b 8 6 1 4 6 d a 2 b 7b 0 n o t e : d a i - l r e g i s t e r i s a l s o u s e d a s l o w - o r d e r 6 b i t s o f d a i l a t c h ( i = 1 , 2 ) . 1 4- b i t p w m c i r c u i t p n 2 p 3 5 p w 1 m s b d a 1 - h r e g i s t e r ( a d d r e s s 0 0 c e 1 6 ) d a 1 l a t c h ( 1 4 b i t s ) d a 1 - l r e g i s t e r ( s e e n o t e ) ( a d d r e s s 0 0 c f 1 6 ) l s b 8 6 1 4 6 d a 1 b 7b 0 46 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 fig. 8.7.2 pwm timing (a) pulses showing the weight of each bit 1 3 5 7 9 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 255 4 12 20 28 36 44 52 60 68 76 84 92 100 108 116 124 132 140 148 156 164 172 180 188 196 204 212 220 228 236 244 252 8 16 48 80 112 144 176 208 240 24 40 56 72 88 104 120 136 152 168 184 200 216 232 248 32 96 160 224 64 192 bit 7 2 6 10 14 18 22 26 30 34 38 42 46 50 54 58 62 66 70 74 78 82 86 90 94 98 102 106 110 114 118 122 126 130 134 138 142 146 150 154 158 162 166 170 174 178 182 186 190 194 198 202 206 210 214 218 222 226 230 234 238 242 246 250 254 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 128 bit 0 pwm output t = 4 m s t = 1024 m s f(x in ) = 8 mhz (b) example of 8-bit pwm t 00 16 (0) 01 16 (1) 18 16 (24) ff 16 (255) t = 256 t 47 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 fig. 8.7.3 14-bit pwm timing (f(x in ) = 8 mhz) 0 . 2 5 m s b 7b 0 b 6b 5b 4b 3b 2b 1 0 0 010110 b 1 3b 6 00 010110 b 0 b 5 101000 s e t 2 c 1 6 t o d a i - h r e g i s t e r . [ d a i - h r e g i s t e r ] d h a t w r i t i n g o f d a i - l b 0 b 6b 5b 4b 3b 2b 1 0 10100 s e t 2 8 1 6 t o d a i - l r e g i s t e r . [ d a i - l r e g i s t e r ] d l a t w r i t i n g o f d a i - l t h e s e b i t s d e c i d e h i g h l e v e l a r e a o f f u n d a m e n t a l w a v e f o r m . t h e s e b i t s d e c i d e s m a l l e r i n t e r v a l t m i n w h i c h h i g h l e v a l a r e a i s [ h i g h l e v e l a r e a o f f u n d a m e n t a l w a v e f o r m + t ] . m i n i m u m r e s o l u t i o n b i t w i d t h 0 . 2 5 m s h i g h - o r d e r 8 - b i t v a l u e o f d a i l a t c h 5 h i g h l e v e l a r e a o f f u n d a m e n t a l w a v e f o r m f f0 0 d 3 f ef d d 6d 40 20 1 d 5 1 4 - b i t p w m o u t p u t 8 - b i t c o u n t e r 0 . 2 5 m s 5 4 4 f f0 0 d 3 f ef dd 6d 40 20 1 d 5 1 4 - b i t p w m o u t p u t 8 - b i t c o u n t e r 0 . 2 5 m s 5 4 5 f u n d a m e n t a l w a v e f o r m w a v e f o r m o f s m a l l e r i n t e r v a l t m s p e c i f i e d b y l o w - o r d e r 6 b i t s f u n d a m e n t a l w a v e f o r m o f s m a l l e r i n t e r v a l t m w h i c h i s n o t s p e c i f i e d b y l o w - o r d e r 6 b i t s i s n o t c h a n g e d . 1 4 - b i t p w m o u t p u t l o w - o r d e r 6 - b i t o u t p u t o f d a i l a t c h 0 . 2 5 m s 5 4 4 t = 0 . 2 5 m s t = 4 0 9 6 m s @ r e p e a t p e r i o d t 0 t 1 t 2 t 3 t 4 t 5 t 5 9 t 6 0 t 6 1 t 6 2 t 6 3 [ d a i l a t c h ] b 7 2 c 2 b 2 a 0 3 0 2 0 10 02 c 2 b 2 a 0 3 0 2 0 10 0 n o t e : i i n d i c a t e s 0 o r 1 . 48 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 fig. 8.7.4 pwm output control register 1 fig. 8.7.5 pwm output control register 2 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 p w m o u t p u t c o n t r o l r e g i s t e r 2 ( p n ) [ a d d r e s s 0 0 d 6 b a f t e r r e s e t rw p w m o u t p u t c o n t r o l r e g i s t e r 2 0 , 1 2 3 4 0 n a m ef u n c t i o n s d a 1 o u t p u t p o l a r i t y s e l e c t i o n b i t ( p n 3 ) 0 : p o s i t i v e p o l a r i t y 1 : n e g a t i v e p o l a r i t y p w m o u t p u t p o l a r i t y s e l e c t i o n b i t ( p n 4 ) f i x t h e s e b i t s t o 0 . d a 2 o u t p u t p o l a r i t y s e l e c t i o n b i t ( p n 5 ) 0 : o u t p u t l o w 1 : o u t p u t h i g h 6 , 7 0 0 0 0 f i x t h e s e b i t s t o 0 . 0 : p o s i t i v e p o l a r i t y 1 : n e g a t i v e p o l a r i t y 1 6 ] r rw rw rw rw 0 0 0 0 5 p 1 7 / d a 2 o u t p u t s e l e c t i o n b i t ( p n 5 ) 0 : p 1 7 1 : d a 2 0 rw w b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 p w m o u t p u t c o n t r o l r e g i s t e r 1 ( p w ) [ a d d r e s s 0 0 d 5 b a f t e r r e s e t rw p w m o u t p u t c o n t r o l r e g i s t e r 1 0 1 2 3 4 0 n a m ef u n c t i o n s d a 1 , d a 2 , p w m c o u n t s o u r c e s e l e c t i o n b i t ( p w 0 ) 0 : c o u n t s o u r c e s u p p l y 1 : c o u n t s o u r c e s t o p p 0 0 / p w m 0 o u t p u t s e l e c t i o n b i t ( p w 2 ) 0 : p 0 0 o u t p u t 1 : p w m 0 o u t p u t p 0 1 / p w m 1 o u t p u t s e l e c t i o n b i t ( p w 3 ) 0 : p 0 1 o u t p u t 1 : p w m 1 o u t p u t p 0 2 / p w m 2 o u t p u t s e l e c t i o n b i t ( p w 4 ) 0 : p 0 2 o u t p u t 1 : p w m 2 o u t p u t 5 p 0 3 / p w m 3 o u t p u t s e l e c t i o n b i t ( p w 5 ) 0 : p 0 3 o u t p u t 1 : p w m 3 o u t p u t 6 p 0 4 / p w m 4 o u t p u t s e l e c t i o n b i t ( p w 6 ) 0 : p 0 4 o u t p u t 1 : p w m 4 o u t p u t d a 1 o u t p u t / p 3 5 s e l e c t i o n b i t ( p w 1 ) 0 : d a 1 o u t p u t 1 : p 3 5 o u t p u t 7 p 0 5 / p w m 5 o u t p u t s e l e c t i o n b i t ( p w 7 ) 0 : p 0 5 o u t p u t 1 : p w m 5 o u t p u t 0 0 0 0 0 0 0 1 6 ] rw rw rw rw rw rw rw rw 49 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 8.8 a-d converter 8.8.1 a-d conversion register (ad) a-d conversion reigister is a read-only register that stores the result of an a-d conversion. this register should not be read during a-d conversion. 8.8.2 a-d control register (adcon) the a-d control register controls a-d conversion. bits 2 to 0 of this register select analog input pins. when these pins are not used as anlog input pins, they are used as ordinary i/o pins. bit 3 is the a-d conversion completion bit, a-d conversion is started by writing 0 to this bit. the value of this bit remains at 0 during an a-d conversion, then changes to 1 when the a-d conversion is completed. bit 4 controls connection between the resistor ladder and v cc . when not using the a-d converter, the resistor ladder can be cut off from the internal v cc by setting this bit to 0, accordingly providing low- power dissipation. 8.8.3 comparison voltage generator (resistor ladder) the voltage generator divides the voltage between v ss and v cc by 256, and outputs the divided voltages to the comparator as the refer- ence voltage v ref . 8.8.4 channel selector the channel selector connects an analog input pin, selected by bits 2 to 0 of the a-d control register, to the comparator. 8.8.5 comparator and control circuit the conversion result of the analog input voltage and the reference voltage v ref is stored in the a-d conversion register. the a-d con- version completion bit and a-d conversion interrupt request bit are set to 1 at the completion of a-d conversion. fig. 8.8.1 a-d converter block diagram a - d c o n t r o l r e g i s t e r ( a d d r e s s 0 0 d f 1 6 ) a - d c o n t r o l c i r c u i t d a t a b u s s w i t c h t r e e a - d c o n v e r s i o n i n t e r r u p t r e q u e s t r e s i s t o r l a d d e r c o m p a - r a t o r c h a n n e l s e l e c t o r a - d c o n v e r s i o n r e g i s t e r a - d1 a - d2 a - d3 a - d4 ( a d d r e s s 0 0 d e 1 6 ) b 7b 0 3 8 v s s v c c a - d5 a - d6 a - d7 a - d8 50 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 fig. 8.8.2 a-d control register a - d c o n t r o l r e g i s t e r b 7b 6b 5b 4b 3b 2b 1b 0 a - d c o n t r o l r e g i s t e r ( a d c o n ) [ a d d r e s s 0 0 d f 1 6 ] b a f t e r r e s e t rw 0 t o 2 a n a l o g i n p u t p i n s e l e c t i o n b i t s ( a d i n 0 t o a d i n 2 ) n a m ef u n c t i o n s b 2 b 1 b 0 0 0 0 : a - d 1 0 0 1 : a - d 2 0 1 0 : a - d 3 0 1 1 : a - d 4 1 0 0 : a - d 5 1 0 1 : a - d 6 1 1 0 : a - d 7 1 1 1 : a - d 8 4 v c c c o n n e c t i o n s e l e c t i o n b i t ( a d v r e f ) 0 : o f f 1 : o n 0 0 6 n o t h i n g i s a s s i g n e d . t h i s b i t i s a w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s i n d e t e r m i n a t e . rw rw r 3 a - d c o n v e r s i o n c o m p l e t i o n b i t ( a d s t r ) 0 : c o n v e r s i o n i n p r o g r e s s 1 : c o n v e r t i o n c o m p l e t e d 1 rw 7 f i x t h i s b i t t o 0 . rw 00 i n d e t e r m i n a t e 5 f i x t h i s b i t t o 0 . rw 0 0 51 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 note: v ref indicates the reference voltage (= vcc). fig. 8.8.3 changes in a-d conversion register and comparison voltage during a-d conversion 8.8.6 conversion method set the a-d conversion interrupt request bit to 0 (even when a- d conversion is started, the a-d conversion interrupt reguest bit is not set to 0 automatically). when using a-d conversion interrupt, enable interrupts by setting a-d conversion interrupt enable bit to 1 and setting the interrupt disable flag to 0. a set the v cc connection selection bit to 1 to connect v cc to the resistor ladder. ? select analog input pins by the analog input selection bit of the a-d control register. ? set the a-d conversion completion bit to 0. this write operation starts the a-d conversion. do not read the a-d conversion regis- ter during the a-d conversion. ? verify the completion of the conversion by the state (1) of the a-d conversion completion bit, the state (1) of a-d conversion interrupt reguest bit, or the occurrence of an a-d conversion in- terrupt. d read the a-d conversion register to obtain the conversion re- sults. note : when the ladder resistor is disconnect from v cc , set the v cc connec- tion selection bit to 0 between steps ? and d . 8.8.7 internal operation when the a-d conversion starts, the following operations are auto- matically performed. the a-d conversion register is set to 00 16 . the most significant bit of the a-d conversion register becomes 1, and the comparison voltage v ref is input to the comparator. at this point, v ref is compared with the analog input voltage v in . a bit 7 is determined by the comparison results as follows. when v ref < v in : bit 7 holds 1 when v ref > v in : bit 7 becomes 0 with the above operations, the analog value is converted into a digital value. the a-d conversion terminates in a maximum of 50 machine cycles (8.5 m s at f(x in ) = 8 mhz) after it starts, and the conversion result is stored in the a-d conversion register. an a-d conversion interrupt request occurs at the same time as a-d conversion completion, the a-d conversion interrupt request bit be- comes 1. the a-d conversion completion bit also becomes 1. table 8.8.1 expression for v ref and v ref a-d conversion register contents n (decimal notation) 0 1 to 255 vref (v) 0 v ref 2 v ref 512 v ref 2 v ref 4 v ref 512 v ref 2 v ref 4 v ref 8 v ref 512 v ref 2 v ref 4 v ref 8 v ref 512 v ref 256 12 3 456 78 1 0000000 12 100000 1000000 1 123456 7 1 00000 000 contents of a-d conversion register reference voltage (v ref ) [v] 0 a-d conversion start 1st comparison start 3rd comparison start 8th comparison start 2nd comparison start digital value corresponding to analog input voltage. a-d conversion completion (8th comparison completion) ....... : value determined by mth (m = 1 to 8) result m ..... v ref 256 ~ (n | 0.5) 52 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 [lsb] [lsb] 8.8.8 definition of a-d conversion accuracy the definition of a-d conversion accuracy is described below (refer to figure 8.8.4). (1) relative accuracy ?zero transition error (v 0t ) the deviation of the input voltage at which a-d conversion output data changes from 0 to 1, from the corresponding ideal a-d conversion characteristics between 0 and v ref . ? non-linearity error the deviation of the actual a-d conversion characteristics, from the ideal a-d conversion characteristics between v 0 and v 254 . (v 0 C 1/2 5 v ref /256) 1lsb v 0t = (v ref C 3/2 5 v ref /256) C v 254 1lsb v fst = non-linearity error = [lsb] [lsb] ? edifferential non-linearity error the deviation of the input voltage required to change output data by 1, from the corresponding ideal a-d conversion characteris- tics between 0 and v ref . (2) absolute accuracy ? eabsolute accuracy error the deviation of the actual a-d conversion characteristics, from the ideal a-d conversion characteristics between 0 and v ref . v n C (1lsb 5 n + v 0 ) 1lsb [lsb] differential non-linearity error = (v n+1 C v n ) C 1lsb 1lsb absolute accuracy error = 1lsb a with respect to absolute accuracy = 1lsb with respect to relative accuracy = note: the analog input voltage vn at which a-d conversion output data changes from n to n + 1 (n ; 0 to 254) is as follows (refer to figure 8.8.4) : v 254 C v 0 254 v ref 256 [v] [v] fig. 8.8.4 definition of a-d conversion accuracy ? full-scale transition error (v fst ) the deviation of the input voltage at which a-d conversion output data changes from 255 to 254, from the corresponding ideal a- d conversion characteristics between 0 and v ref . v n C 1lsb a 5 (n + 1/2) 1lsb a output code 0 analog input voltage (mv) 20 40 80 100 120 140 160 180 200 220 00 16 01 16 02 16 03 16 04 16 05 16 06 16 07 16 08 16 09 16 + 2lsb C 2lsb 60 absolute accuracy limitless resolution a-d conversion characteristics ideal a-d conversion characteristics 53 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 fig. 8.9.2 rom correction enable register fig. 8.9.1 rom correction address registers 8.9 rom correction function this can correct program data in rom. up to 3 addresses can be corrected, a program for correction is stored in the rom correction vector in ram as the top address. the rom correction vectors are 3 vectors. vector 1 : address 02c0 16 vector 2 : address 02e0 16 vector 3 : address 0300 16 set the address of the rom data to be corrected into the rom cor- rection address register. when the value of the counter matches the rom data address in the rom correction vector as the top address, the main program branches to the correction program stored in the rom memory for correction. to return from the correction program to the main program, the op code and operand of the jmp instruction (total of 3 bytes) are necessary at the end of the correction program. the rom correction function is controlled by the rom correction enable register. notes 1: specify the first address (op code address) of each instruction as the rom correction address. 2: use the jmp instruction (total of 3 bytes) to return from the correction program to the main program. 3: do not set the same rom correction address to vectors 1 to 3. 0 2 1 7 1 6 r o m c o r r e c t i o n a d d r e s s 1 ( h i g h - o r d e r ) 0 2 1 8 1 6 r o m c o r r e c t i o n a d d r e s s 1 ( l o w - o r d e r ) 0 2 1 9 1 6 r o m c o r r e c t i o n a d d r e s s 2 ( h i g h - o r d e r ) 0 2 1 a 1 6 r o m c o r r e c t i o n a d d r e s s 2 ( l o w - o r d e r ) 0 2 1 c 1 6 r o m c o r r e c t i o n a d d r e s s 3 ( h i g h - o r d e r ) 0 2 1 d 1 6 r o m c o r r e c t i o n a d d r e s s 3 ( l o w - o r d e r ) b 7b 6b 5b 4b 3b 2b 1b 0 r o m c o r r e c t i o n e n a b l e r e g i s t e r ( r c r ) [ a d d r e s s 0 2 1 b 1 6 ] b a f t e r r e s e t rw r o m c o r r e c t i o n e n a b l e r e g i s t e r 0 v e c t o r 1 e n a b l e b i t ( r c r 0 ) n a m ef u n c t i o n s 0 : d i s a b l e d 1 : e n a b l e d 0 rw 1 v e c t o r 2 e n a b l e b i t ( r c r 1 ) 0 : d i s a b l e d 1 : e n a b l e d 0 rw 0 3 t o 7 f i x t h e s e b i t s t o 0 . 0 rw 0 0 0 0 2 v e c t o r 3 e n a b l e b i t ( r c r 2 ) 0 : d i s a b l e d 1 : e n a b l e d 0 rw 54 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 8.10 osd functions this osd function can display the following 3 types: ? block display (24 characters 5 2 lines) ? sprite display (display only a character) or raster patterning display (display a character on entire screen side by side) ? raster flat display (coloring entire screen) the above displays can be overlapped at the same time. the priority is : sprite display > block display > raster flat display or block display > raster patterning display > raster flat display note that raster patterning display and sprite display cannot be used simultaneously. figure 8.10.2 shows the block diagram of osd circuit, figure 8.10.3 shows the configuration of osd character display area, figure 8.10.4 shows the osd control register. fig. 8.10.1 display types of osd function o s d f u n c t i o n d d i i s s p p l l a a y y t t y y p p e e d d i i s s p p l l a a y y m m o o d d e e s p r i t e d i s p l a y ( s e e n o t e ) b l o c k d i s p l a y o s d m o d e b u t t o n m o d e d d i i s s p p l l a a y y l l e e v v e e l l ( ( d d i i s s p p l l a a y y p p r r i i o o r r i i t t y y ) ) t o p m i d d l e a l l b o r d e r e d s h a d o w b o r d e r e d i i n n t t e e r r r r u u p p t t r r e e q q u u e e s s t t s p r i t e o s d i n t e r r u p t o s d i n t e r r u p t b o t t o m n o t e : r a s t e r p a t t e r n i n g d i s p l a y a n d s p r i t e d i s p l a y c a n n o t b e u s e d s i m u l t a n e o u s l y . r a s t e r f l a t d i s p l a y a l l b o r d e r e d s h a d o w b o r d e r e d r a s t e r p a t t e r n i n g d i s p l a y ( s e e n o t e ) t o p m i d d l e b o t t o m ( s e e n o t e ) 55 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 fig. 8.10.2 block diagram of osd circuit d i s p l a y o c s i l l a t i o n c i r c u i t o s c 1 h s y n c v s y n c o s d r a m 1 5 b i t s 5 2 4 c h a r a c t e r s 5 2 l i n e s d a t a b u s o s d r o m 1 6 d o t s 5 2 0 d o t s 5 3 8 1 c h a r a c t e r s s h i f t r e g i s t e r m a i n c l o c k x i n c l o c k f o r o s d o u t p u t c i r c u i t r g b o s d c o n t r o l c i r c u i t o u t 1 c o n t r o l r e g i s t e r s f o r o s d o s d p o r t c o n t r o l r e g i s t e r i n t e r r u p t i n p u t p o l a r i t y r e g i s t e r b l o c k h r e g i s t e r b l o c k i v r e g i s t e r s p r i t e c o n t r o l r e g i s t e r s p r i t e h r e g i s t e r s p r i t e v r e g i s t e r c o l o r r e g i s t e r i o s d c o n t r o l r e g i s t e r o s d i / o p o l a r i t y r e g i s t e r b l o c k i c o n t r o l r e g i s t e r l e f t b o r d e r r e g i s t e r r i g h t b o r d e r r e g i s t e r t o p b o r d e r r e g i s t e r b o t t o m b o r d e r r e g i s t e r ( a d d r e s s 0 0 c b 1 6 ) ( a d d r e s s 0 0 c d 1 6 ) ( a d d r e s s 0 0 e 0 1 6 ) ( a d d r e s s e s 0 0 e 1 1 6 , 0 0 e 2 1 6 ) ( a d d r e s s 0 0 e 3 1 6 j ( a d d r e s s 0 0 e 4 1 6 ) ( a d d r e s s 0 0 e 5 1 6 ) ( a d d r e s s e s 0 0 e 6 1 6 t o 0 0 e 9 1 6 , 0 0 e c 1 6 t o 0 0 e f 1 6 ) ( a d d r e s s 0 0 e a 1 6 ) ( a d d r e s s 0 0 e b 1 6 ) ( a d d r e s s e s 0 0 f 9 1 6 , 0 0 f a 1 6 ) ( a d d r e s s 0 2 4 0 1 6 ) ( a d d r e s s 0 2 4 1 1 6 ) ( a d d r e s s 0 2 4 5 1 6 ) ( a d d r e s s 0 2 4 6 1 6 ) o u t 2 56 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 fig. 8.10.3 configuration of osd character display area 1 6 d o t s 2 0 d o t s 1 6 d o t s 2 0 d o t s b l o c k d i s p l a y ( o s d m o d e ) b l o c k d i s p l a y ( b u t t o n m o d e ) s p r i t e d i s p l a y : b u t t o n d i s p l a y a r e a ( d i s p l a y e d o n l y i n b u t t o n m o d e j 2 d o t s 2 d o t s fig. 8.10.4 osd control register b 3b 2( s e e n o t e s 3 a n d 4 ) 00 : s t a n d a r d 01 : s t a n d a r d + 1 t o s c 10 : s t a n d a r d + 2 t o s c 11 : s t a n d a r d + 3 t o s c b 7b 6b 5b 4b 3b 2b 1b 0 o s d c o n t r o l r e g i s t e r ( o c ) [ a d d r e s s 0 0 e a 1 6 ] bn a m e f u n c t i o n s a f t e r r e s e t r w o s d c o n t r o l r e g i s t e r 0 o s d c o n t r o l b i t ( o c 0 ) ( s e e n o t e 1 ) 0 : a l l - b l o c k s d i s p l a y o f f 1 : a l l - b l o c k s d i s p l a y o n 0 1 b o r d e r t y p e s e l e c t i o n b i t ( o c 1 ) 0 : a l l b o r d e r e d 1 : s h a d o w b o r d e r e d ( s e e n o t e 2 ) 0 2 , 3 0 4w i n d o w c o n t r o l b i t ( o c 4 ) 0 w i n d o w h o r i z o n t a l p o s i t i o n m i n u t e a d j u s t m e n t b i t ( o c 2 , o c 3 ) rw rw rw rw 6r a s t e r c o l o r o u t 1 c o n t r o l b i t ( o c 6 ) 0 : w i n d o w o f f 1 : w i n d o w o n 0rw 5 s c a n m o d e s e l e c t i o n b i t ( o c 5 ) 0rw 0 : n o r m a l s c a n m o d e 1 : b i - s c a n m o d e ( s e e n o t e 5 ) n o t e s 1 : e v e n t h i s b i t i s s w i t c h e d d u r i n g d i s p l a y , t h e d i s p l a y s c r e e n r e m a i n s u n c h a n g e d u n t i l a r i s i n g ( f a l l i n g ) o f t h e n e x t v s y n c . 2 : s h a d o w b o r d e r i s o u t p u t a t r i g h t a n d b o t t o m s i d e o f t h e f o n t . 3 : t o s c = o s d o s c i l l a t i o n c y c l e 4 : t h e s e b i t s a r e v a l l i d f o r b o t h l e f t b o r d e r a n d r i g h t b o r d e r ( f o r d e t a i l , r e f e r t o ( 8 ) w i n d o w f u n c t i o n . ) 5 : w h e n s e t t i n g t o b i - s c a n m o d e , c o n n e c t l c b e t w e e n p i n s o s c 1 a n d o s c 2 . 0 : n o o u t p u t 1 : o u t p u t 7r a s t e r c o l o r o u t 2 c o n t r o l b i t ( o c 7 ) 0rw 0 : n o o u t p u t 1 : o u t p u t 57 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 (1) clock for osd as a clock for display to be used for osd, it is possible to select one of the following 3 types. ? main clock from the pins x in and x out ? clock from the lc or rc oscillator supplied from the pins osc1 and osc2 ? clock from the ceramic resonator or the quartz-crystal oscillator from the pins osc1 and osc2 the clock for display to be used for osd can be selected by bits 0 and 1 of the interrupt input polarity register (address 00cd 16 ). and besides, when selecting main clock, set the oscillation frequency to 8 mhz. fig. 8.10.5 interrupt input polarity register b 7b 6b 5b 4b 3b 2b 1b 0 i n t e r r u p t i n p u t p o l a r i t y r e g i s t e r ( i p ) [ a d d r e s s 0 0 c d 1 6 ] bn a m ef u n c t i o n a f t e r r e s e t r w i n t e r r u p t i n p u t p o l a r i t y r e g i s t e r 0 0 i n t 1 p o l a r i t y s w i t c h b i t ( p o l 1 ) 2 3 4 5 0 : p o s i t i v e p o l a r i t y 1 : n e g a t i v e p o l a r i t y 6 , 7 0r w 0r w 0r w i n t 2 p o l a r i t y s w i t c h b i t ( p o l 2 ) i n t 3 p o l a r i t y s w i t c h b i t ( p o l 3 ) f i x t h e s e b i t s t o 0 . 0w r 0w r 0 , 1 o s d c l o c k s e l e c t i o n b i t s ( o c g 0 , o c g 1 ) 0 r w s i n c e t h e m a i n c l o c k i s u s e d a s t h e c l o c k f o r o s d , t h e o s c i l l a t i o n f r e q u e n c y i s l i m i t e d . b e c a u s e o f t h i s , t h e c h a r a c t e r s i z e i n w i d t h ( h o r i z o n a l ) d i r e c t i o n i s a l s o l i m i t e d . i n t h i s c a s e , p i n s o s c 1 a n d o s c 2 a r e a l s o u s e d a s i n p u t p o r t s p 3 3 a n d p 3 4 r e s p e c t i v e l y . t h e c l o c k f o r o s d i s s u p p l i e d b y c o n n e c t i n g t h e f o l l o w i n g a c r o s s t h e p i n s o s c 1 a n d o s c 2 . h o w e v e r , i t i s n o t c o r r e s p o n d i n g t o t h e b i - s c a n m o d e . a c e r a m i c r e s o n a t o r o n l y f o r o s d a n d a f e e d b a c k r e s i s t o r a q u a r t z - c r y s t a l o s c i l l a t o r o n l y f o r o s d a n d a f e e d b a c k r e s i s t o r b 1 t h e c l o c k f o r o s d i s s u p p l i e d b y c o n n e c t i n g r c o r l c a c r o s s t h e p i n s o s c 1 a n d o s c 2 . h o w e v e r , i t i s n o t c o r r e s p o n d i n g t o t h e b i - s c a n m o d e . f u n c t i o n 00 b 0 o s d o s c i l l a t i o n f r e q u e n c y = f ( x i n ) 0 0 1 1 11 t h e c l o c k f o r o s d i s s u p p l i e d b y c o n n e c t i n g l c a c r o s s t h e p i n s o s c 1 a n d o s c 2 . i n t h e b i - s c a n m o d e , b e s u r e t o s e t t h i s . f i x t h i s b i t t o 0 . 0 : p o s i t i v e p o l a r i t y 1 : n e g a t i v e p o l a r i t y 0 : p o s i t i v e p o l a r i t y 1 : n e g a t i v e p o l a r i t y 0 58 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 (2) scan mode this microcomputer has the bi-scan mode for corresponding to h sync of double-speed frequency. in the bi-scan mode, the vertical start display position and the vertical dot size is two times as compared with the normal scan mode. the scan mode is selected by bit 5 of the osd control register (refer to figure 8.10.3). parameter bit 5 of osd control register vertical display start position vertical dot size table 8.10.1 setting for scan mode normal scan 0 value of vertical position register 5 1h 1t osc 5 1h 2t osc 5 2h 3t osc 5 3h bi-scan 1 value of vertical position register 5 2h 1t osc 5 2h 2t osc 5 4h 3t osc 5 6h scan mode notes 1: t osc = osd oscillation cycle 2: h = h sync 59 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 (3) osd input/output pin control the osd output pins r, g, b, out1 and out2 can also function as ports p5 2 , p5 3 , p5 4 , p5 5 , p1 0 respectively. switch either osd out- put function or port function by the osd port control register (ad- dress 00cb 16 ). the input polarity of the h sync , v sync and output polarity of signals r, g, b, out1 and out2 can be specified with the osd i/o polarity register (address 00eb 16 ). set a bit to 0 to specify positive polarity; fig. 8.10.6 osd i/o polarity register b 7b 6b 5b 4b 3b 2b 1b 0 o s d i / o p o l a r i t y r e g i s t e r ( o p c ) [ a d d r e s s 0 0 e b 1 6 ] b n a m ef u n c t i o n s a f t e r r e r w o s d i / o p o l a r i t y r e g i s t e r 0h s y n c i n p u t p o l a r i t y s w i t c h b i t ( o p c 0 ) 0 : p o s i t i v e p o l a r i t y i n p u t 1 : n e g a t i v e p o l a r i t y i n p u t 0 1 0 : p o s i t i v e p o l a r i t y i n p u t 1 : n e g a t i v e p o l a r i t y i n p u t 0 2r / g / b o u t p u t p o l a r i t y s w i t c h b i t ( o p c 2 ) 0 : p o s i t i v e p o l a r i t y o u t p u t 1 : n e g a t i v e p o l a r i t y o u t p u t 0 3 0 v s y n c i n p u t p o l a r i t y s w i t c h b i t ( o p c 1 ) r w r w r w r w 4 o u t 2 o u t p u t p o l a r i t y s w i t c h b i t ( o p c 4 ) 0 : p o s i t i v e p o l a r i t y o u t p u t 1 : n e g a t i v e p o l a r i t y o u t p u t 0 5r a s t e r c o l o r r c o n t r o l b i t ( o p c 5 ) 0 : n o o u t p u t 1 : o u t p u t 0 6r a s t e r c o l o r g c o n t r o l b i t ( o p c 6 ) 0 7r a s t e r c o l o r b c o n t r o l b i t ( o p c 7 ) 0 : n o o u t p u t 1 : o u t p u t 0 r w r w r w r w o u t 1 o u t p u t p o l a r i t y s w i t c h b i t ( o p c 3 ) 0 : p o s i t i v e p o l a r i t y o u t p u t 1 : n e g a t i v e p o l a r i t y o u t p u t 0 : n o o u t p u t 1 : o u t p u t set it to 1 to specify negative polarity. figure 8.10.6 shows the osd i/o polarity register and figure 8.10.7 shows the osd port control register. fig. 8.10.7 osd port control register b 7b 6b 5b 4b 3b 2b 1b 0 o s d p o r t c o n t r o l r e g i s t e r ( p f ) [ a d d r e s s 0 0 c b 1 6 ] bn a m ef u n c t i o n s a f t e r r e s e t r w o s d p o r t c o n t r o l r e g i s t e r 0 , 10 r w f i x t h e s e b i t s t o 0 00 2 0 : r s i g n a l o u t p u t 1 : p o r t p 5 2 o u t p u t 0 r w 3p o r t p 5 3 o u t p u t s i g n a l s e l e c t i o n b i t ( p 5 3 s e l ) 0 : g s i g n a l o u t p u t 1 : p o r t p 5 3 o u t p u t 0 r w 4p o r t p 5 4 o u t p u t s i g n a l s e l e c t i o n b i t ( p 5 4 s e l ) 0 : b s i g n a l o u t p u t 1 : p o r t p 5 4 o u t p u t 0 r w 5p o r t p 5 5 o u t p u t s i g n a l s e l e c t i o n b i t ( p 5 5 s e l ) 0 : o u t 1 s i g n a l o u t p u t 1 : p o r t p 5 5 o u t p u t 0 r w 6p o r t p 1 0 o u t p u t s i g n a l s e l e c t i o n b i t ( o u t 2 s e l ) 0 : p o r t p 1 0 s i g n a l o u t p u t 1 : o u t 2 o u t p u t 0 r w p o r t p 5 2 o u t p u t s i g n a l s e l e c t i o n b i t ( p 5 2 s e l ) 70 r w f i x t h i s b i t t o 0 0 60 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 fig. 8.10.8 block i control register (i = 1, 2) b 2b 1b 0d i s p l a y m o d e 5 00d i s p l a y o f f 00 1 o s d m o d e ( n o b o r d e r ) 01 0 b u t t o n m o d e ( n o b o r d e r ) 10 1 o s d m o d e ( b o r d e r ) 11 0 b u t t o n m o d e ( b o r d e r ) b 7b 6b 5b 4b 3b 2b 1b 0 b l o c k i c o n t r o l r e g i s t e r ( b i c ) ( i = 1 , 2 ) [ a d d r e s s e s 0 0 f 9 1 6 , 0 0 f a 1 6 ] bn a m e f u n c t i o n s a f t e r r e s e t r w b l o c k i c o n t r o l r e g i s t e r 0 t o 2 d i s p l a y m o d e s e l e c t i o n b i t s ( b i c 0 t o b i c 2 ) i n d e t e r m i n a t e 3, 4 d o t s i z e s e l e c t i o n b i t ( b i c 3 , b i c 4 ) rw rw n o t e s 1 : t o s c = o s d o s c i l l a t i o n c y c l e 2 : h = h s y nc b 4b 3d o t s i z e 00 1 t o s c 5 1 h 01 d o n o t s e t 10 2 t o s c 5 2 h 11 3 t o s c 5 3 h 5 t o 7 0 n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . r i n d e t e r m i n a t e 8.10.1 block display there are 2 display modes and they are selected by a block unit. the display modes are selected by bits 0 to 2 of block i control register (i = 1, 2). the features of each mode are described below. there are an extended display mode. this mode allows multiple lines (3 lines or more) to be displayed on the screen by interrupting the display each time one line is displayed and rewriting data in the block for which display is terminated by software. table 8.10.2 features of each display style of block display 1 s c r e e n : 8 k i n d s ( p e r c h a r a c t e r u n i t ) k i n d s o f c h a r a c t e r s i z e s d o t s i z e a t t r i b u t e c h a r a c t e r f o n t c o l o r i n g c h a r a c t e r b a c k g r o u n d c o l o r i n g n o t e s 1 : t o s c = o s d o s c i l l a t i o n c y c l e 2 : h = h s y n c 3: t h e s p r i t e d i s p l a y i s n o t e f f e c t e d b y t h e w i n d o w f u n c t i o n . o s d m o d e ( o n - s c r e e n d i s p l a y m o d e ) b l o c k d i s p l a y b u t t o n m o d e ( b u t t o n d i s p l a y m o d e ) d i s p l a y s t y l e p a r a m e t e r n u m b e r o f d i s p l a y c h a r a c t e r s 2 4 c h a r a c t e r s 5 2 l i n e s d o t s t r u c t u r e k i n d s o f c h a r a c t e r s 3 8 1 k i n d s b o r d e r ( p e r b l o c k u n i t ) 3 k i n d s 1 t o s c 5 1 h , 2 t o s c 5 2 h , 3 t o s c 5 3 h ( p e r b l o c k u n i t ) ( s e e n o t e s 1 , 2 ) 1 6 5 2 0 d o t s c h a r a c t e r d i s p l a y a r e a : ( 1 6 d o t s + 4 d o t s ) ( 2 0 d o t s + 4 d o t s ) 1 s c r e e n : 8 k i n d s ( p e r c h a r a c t e r u n i t ) o s d o u t p u t r , g , b d i s p l a y e x p a n s i o n ( m u l t i l i n e d i s p l a y ) p o s s i b l e d i s p l a y p o s i t i o nh o r i z o n t a l : 6 4 l e v e l s , v e r t i c a l : 2 5 5 l e v e l s d i s p l a y m o d e n b o r d e r ( p e r b l o c k u n i t ) n b u t t o n d i s p l a y ( p e r c h a r a c t e r u n i t ) n b l o c k s h a d o w d i s p l a y ( p e r c h a r a c t e r u n i t ) r a s t e r c o l o r i n gp o s s i b l e ( p e r s c r e e n u n i t ) o t h e r fu n c t i o n s n c o r r e s p o n d i n g t o b i - s c a n n w i n d o w f u n c t i o n ( s e e n o t e 3 ) 1 6 5 2 0 d o t s 5 61 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 (1) display position the display positions of characters are specified by a block. there are 2 blocks, blocks 1 and 2. up to 24 characters can be displayed in each block (refer to (3) memory for osd). the display position of each block can be set in both horizontal and vertical directions by software. the display start position in the horizontal direction can be set for all blocks in common in 64-step display positions in units of 4t osc (t osc = osd oscillation cycle). the display start position in the vertical direction for each block can be set in 255-step display positions in units of 1 h ( h = h sync cycle). blocks are displayed in conformance with the following rules: ? when the display position of block 1 is overlapped with block 2 (figure 8.10.9 (b)), block 1 is displayed on the front. ? when another block display position appears while one block is . displayed (figure 8.10.9 (c)), the block with a larger set value as the vertical display start position is displayed. for the display position of sprite display, it is necessary to set in- dependently, and it is possible to set display positions independently. refer to 8.10.2 sprite display. fig. 8.10.9 display position b h p b 2 v p b l o c k 1 b l o c k 2 ( a ) e x a m p l e w h e n e a c h b l o c k i s s e p a r a t e d b h p b 1 v p = b 2 v p b l o c k 1 ( b ) e x a m p l e w h e n b l o c k 2 o v e r l a p s w i t h b l o c k 1 ( b l o c k 2 i s n o t d i s p l a y e d ) b h p b 1 v p b 2 v p ( c ) e x a m p l e w h e n b l o c k 2 o v e r l a p s i n p r o c e s s o f b l o c k 1 b l o c k 1 b l o c k 2 n o t e s 1 : b 1 v p o r b 2 v p i n d i c a t e s t h e v e r t i c a l d i s p l a y s t a r t p o s i t i o n o f d i s p l a y b l o c k s 1 a n d 2 . 2: b h p i n d i c a t e s t h e h o r i z o n t a l d i s p l a y s t a r t p o s i t i o n o f d i s p l a y b l o c k s 1 a n d 2 . b 1 v p 62 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 the vertical display start position is determined by counting the hori- zontal sync signal (h sync ). at this time, when v sync and h sync are positive polarity (negative polarity), it starts to count the rising edge (falling edge) of h sync signal from after fixed cycle of rising edge (falling edge) of v sync signal. so interval from rising edge (falling edge) of v sync signal to rising edge (falling edge) of h sync signal needs enough time (2 machine cycles or more) for avoiding jitter. the polarity of h sync and v sync signals can select with the osd i/ o polarity register (address 00eb 16 ). fig. 8.10.10 supplement explanation for display position w h e n b i t s 0 a n d 1 o f t h e i / o p o l a r i t y c o n t r o l r e g i s t e r ( a d d r e s s 0 0e b 1 6 ) a r e s e t t o 1 ( n e g a t i v e p o l a r i t y ) v s y n c s i g n a l i n p u t v s y n c c o n t r o l s i g n a l i n m i c r o c o m p u t e r 0 . 2 5 t o 0 . 5 0 [ m s ] ( a t f ( x i n ) = 8 m h z ) ( s e e n o t e 2 ) n o t c o u n t 12345 n o t e s 1 : t h e v e r t i c a l p o s i t i o n i s d e t e r m i n e d b y c o u n t i n g f a l l i n g e d g e o f h s y n c s i g n a l a f t e r r i s i n g e d g e o f v s y n c c o n t r o l s i g n a l i n t h e m i c r o c o m p u t e r . 2 : d o n o t g e n e r a t e f a l l i n g e d g e o f h s y n c s i g n a l n e a r r i s i n g e d g e o f v s y n c c o n t r o l s i g n a l i n m i c r o c o m p u t e r t o a v o i d j i t t e r . 3 : t h e p u l s e w i d t h o f v s y n c a n d h s y n c n e e d s 8 m a c h i n e c y c l e s o r m o r e . 8 m a c h i n e c y c l e s o r m o r e 8 m a c h i n e c y c l e s o r m o r e h s y n c s i g n a l i n p u t p e r i o d o f c o u n t i n g h s y n c s i g n a l fig. 8.10.11 block i v register (i = 1, 2) the vertical display start position for each block can be set in 255 steps (where each step is 1h (h: h sync cycle)) as values 01 16 to ff 16 in block i v register (i = 1, 2) (addresses 00e1 16 to 00e2 16 ). when setting the block i v register to 01 16 , the display is started at 18h of count value of h sync signal. the vertical display start posi- tion here indicates the top position of character display area in osd/ button mode. the block i v register is shown in figures 8.10.11. b 7b 6b 5b 4b 3b 2b 1b 0 b l o c k i v r e g i s t e r ( b i v p ) ( i = 1 , 2 ) [ a d d r e s s e s 0 0 e 1 1 6 a n d 0 0 e 2 1 6 ] bn a m ef u n c t i o n sa f t e r r e s e tr w b l o c k i v r e g i s t e r 0 t o 7 c o n t r o l b i t s o f v e r t i c a l d i s p l a y s t a r t p o s i t i o n s ( b i v p 0 t o b i v p 7 ) ( s e e n o t e 1 ) i n d e t e r m i n a t e rw n o t e : s e t v a l u e s e x c e p t 0 0 1 6 t o b i v p . v e r t i c a l d i s p l a y s t a r t p o s i t i o n s = h d e f + h 5 n ( n : s e t t i n g v a l u e , h d e f : 1 7 h , h : h s y n c ) 63 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 the horizontal display start position is common to all blocks, and can be set in 64 steps (where 1 step is 4t osc , t osc being the osd oscillation cycle) as values 00 16 to 3f 16 in the block h register (address 00e0 16 ). the block h register is shown in figure 8.10.13. fig. 8.10.13 block h register b 7b 6b 5b 4b 3b 2b 1b 0 h o r i z o n t a l p o s i t i o n r e g i s t e r ( h p ) [ a d d r e s s 0 0 e 0 1 6 ] bn a m ef u n c t i o n s b l o c k h r e g i s t e r c o n t r o l b i t s o f h o r i z o n t a l d i s p l a y s t a r t p o s i t i o n s ( b h p 0 t o b h p 5 ) ( s e e n o t e 1 ) 0 t o 5 n o t e : t h e s e t t i n g v a l u e s y n c h r o n i z e s w i t h t h e v s y n c . 6 , 7 n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . a f t e r r e s e t rw 0rw 0r h o r i z o n t a l d i s p l a y s t a r t p o s i t i o n s = t d e f 1 + 4 t o s c 5 n ( n : s e t t i n g v a l u e , t d e f 1 : 3 1 t o s c , t o s c : o s d o s c i l l a t i o n c y c l e ) fig. 8.10.12 notes on vertical display start position n v : v a l u e o f b l o c k v r e g i s t e r i ( d e c i m a l ) h d e f : 1 7 h v s y n c ( w h e n s e t t i n g 0 1 1 6 ? t o b l o c k i v r e g i s t e r , v e r t i c a l d i s p l a y s t a r t p o s i t i o n f o r e a c h m o d e ) s c r e e n h s y n c h d e f n v 1 2 3 1 7 1 8 o s d m o d eb u t t o n m o d e v e r t i c a l d i s p l a y s t a r t p o s i t i o n w h e n b i t s 0 a n d 1 o f o s d i / o p o l a r i t y r e g i s t e r ( a d d r e s s 0 0 e b 1 6 ) a r e 1 ( n e g a t i v e p o l a r i t y ) 64 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 fig. 8.10.14 notes on horizontal display start position h s y n c h o r i z o n t a l d i s p l a y s t a r t p o s i t i o n 4 t o s c 5 n h t d e f 1 b u t t o n m o d e ( 1 t o s c 5 1 h ) b u t t o n m o d e ( 2 t o s c 5 2 h ) n h : v a l u e o f b l o c k h r e g i s t e r ( d e c i m a l ) t o s c : o s d o s c i l l a t i o n c y c l e t d e f 1 : 3 1 t o s c w i d t h o f b u t t o n d i s p l a y a r e a ( 2 d o t s ) o s d m o d e b u t t o n m o d e ( 3t o s c 5 3 h ) when setting the block h register to 00 16 , it needs 31t osc (= t def1 ) from a rising edge (negative polarity) of h sync signal to horizontal display start position. the horizontal display start position here indi- cates the left position of the 1st characters button display area in button mode. when also changing character size, the horizontal display start position is the same. in osd mode, display position is shifted for button display area (for 2 dots) from that of the same character size in button mode. 65 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 (2) dot size the dot size can be selected by a block unit. the dot size in vertical direction is determined by dividing h sync in the vertical dot size con- trol circuit. the dot size in horizontal is determined by dividing the following clock in the horizontal dot size control circuit : the clock gained by dividing the osd clock source (osc1, main clock from pin x in ) in the pre-divide circuit. the dot size is specified by bits 3 and 4 of the block i control register. fig. 8.10.15 block diagram of dot size control circuit fig. 8.10.16 definition of dot sizes refer to figure 8.10.8 (the block i control register). the block diagram of dot size control circuit is shown in figure 8.10.15. 1 d o t 1 h s c a n n i n g l i n e o f f 1 ( f 2 ) s c a n n i n g l i n e o f f 2 ( f 1 ) 2 h 3 h 3 t o s c 2 t o s c 1 t o s c o s d c o n t r o l c i r c u i t s y n c h r o n o u s c i r c u i t h o r i z o n t a l d o t s i z e c o n t r o l c i r c u i t m a i n c l o c k x i n h s y n c o s c 1 o c g 0 = 1 v e r t i c a l d o t s i z e c o n t r o l c i r c u i t c l o c k c y c l e = 1 t o s c o c g 1 = 0 66 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 (3) memory for osd there are 2 types of memory for osd : osd rom (addresses 11400 16 to 13bff 16 and 15400 16 to 17aff 16 ) used to specify character dot data and osd ram (addresses 0800 16 to 0877) used to specify the characters, colors, and attribute. the following describes each type of memory. fig. 8.10.17 character font data storing address osd rom (addresses 11400 16 to 13bff 16 , 15400 16 to 17aff 16 ) the dot pattern data for osd characters is stored in the charac- ter font area in the osd rom. to specify the kinds of the char- acter font, it is necessary to write the character code (based on osd rom address) into the osd ram. the modes are selected by bit 3 of the osd control register 3 for each screen. the character font data storing address is shown in figure 8.10.17. o s d r o m a d d r e s s o f c h a r a c t e r f o n t d a t a a d 1 6 a d 1 5 a d 1 4 a d 1 3 a d 1 2a d 1 1a d 1 0 a d 9 a d 8 a d 7 a d 6 a d 5 a d 4 a d 3 a d 2a d 1a d 0 o s d r o m a d d r e s s b i t 1l i n e n u m b e r f o n t b i t l i n e n u m b e r / c h a r a c t e r c o d e / f o n t b i t c h a r a c t e r c o d e ( l o w - o r d e r 8 b i t s ) 0 l i n e n u m b e r = 0 a 1 6 t o 1 d 1 6 c h a r a c t e r c o d e = 0 0 0 1 6 t o 1 7 f 1 6 ( 0 7 f 1 6 , 0 8 0 1 6 a n d 1 7 f 1 6 c a n n o t b e u s e d . ) f o n t b i t = 0 : l e f t a r e a 1 : r i g h t a r e a c h a r a c t e r c o d e ( h i g h - o r d e r 1 ) c h a r a c t e r f o n t l i n e n u m b e r o s d r o m d a t a 0 0 0 0 1 6 7 f f 0 1 6 7 f f 8 1 6 6 0 1 c 1 6 6 0 0 c 1 6 6 0 0 c 1 6 6 0 0 c 1 6 6 0 0 c 1 6 6 0 1 c 1 6 7 f f 8 1 6 7 f f 0 1 6 6 3 0 0 1 6 6 3 8 0 1 6 6 1 c 0 1 6 6 0 e 0 1 6 6 0 7 0 1 6 6 0 3 8 1 6 6 0 1 c 1 6 6 0 0 c 1 6 0 0 0 0 1 6 l e f t a r e ar i g h t a r e a b 0 b 7b 0 b 7 0 a 1 1 0 b 0 c 0 d 0 e 0 f 1 0 1 2 1 9 1 3 1 4 1 5 1 6 1 7 1 8 1 d 1 a 1 b 1 c 67 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 1st character 2nd character 3rd character : 16th character 17st character : 24nd character 1st character 2nd character 3rd character : 16th character 17st character : 24nd character note: the 120-byte addresses corresponding to the character code 07f 16 , 080 16 and 17f 16 in osd rom are the test data storing area. set ff 16 to the area. (we stores the test data to this area and the different data from ff 16 is stored for the actual products.) 68 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 fig. 8.10.18 structure of osd ram c h a r a c t e r c o d e c o l o r c o d e n o t u s e d o u t 2 c o n t r o l f i x t o 0 ch a r a c t e r c o d e i n o s d r o m r a 3r a 2r a 1 00 0 :c o l o r r e g i s t e r 1 00 1 :c o l o r r e g i s t e r 2 01 0 :c o l o r r e g i s t e r 3 01 1 :c o l o r r e g i s t e r 4 10 0 :c o l o r r e g i s t e r 5 10 1 :c o l o r r e g i s t e r 6 11 0 :c o l o r r e g i s t e r 7 11 1 :c o l o r r e g i s t e r 8 0 : o u t 2 b l a n k o u t p u t o f f 1 : o u t 2 b l a n k o u t p u t o n ch a r a c t e r c o d e i n o s d r o m r a 3r a 2r a 1 00 0 :c o l o r r e g i s t e r 1 00 1 :c o l o r r e g i s t e r 2 01 0 :c o l o r r e g i s t e r 3 01 1 :c o l o r r e g i s t e r 4 10 0 :c o l o r r e g i s t e r 5 10 1 :c o l o r r e g i s t e r 6 11 0 :c o l o r r e g i s t e r 7 11 1 :c o l o r r e g i s t e r 8 r a 4r a 4 00 : n o b u t t o n / b l o c k s h a d o w d i s p l a y 01 :o n b u t t o n d i s p l a y 10 :o f f b u t t o n d i s p l a y 01 :b l o c k s h a d o w d i s p l a y 0 : o u t 2 b l a n k o u t p u t o f f 1 : o u t 2 b l a n k o u t p u t o n c h a r a c t e r c o d e c o l o r c o d e a t t r i b u t e c o d e o u t 2 c o n t r o l f i x t o 0 b l o c k s 1 a n d 2 b u t t o n m o d e b i t n a m ef u n c t i o n b i t m o d e r f 0 r f 1 r f 2 r f 3 r f 4 r f 5 r f 6 r f 7 r f 8 r a 1 r a 2 r a 3 r a 4 r a 5 r a 6 r a 7 o s d m o d e n o t e s 1 : a t t r i b u t e c o d e i s v a l i d i n o n l y b u t t o n m o d e . 2 : d o n o t u s e c h a r a c t e r c o d e s 0 7 f 1 6 , 0 8 0 1 6 , 1 7 f 1 6 . a n d a l s o , d o n o t u s e c h a r a c t e r c o d e s 1 8 0 1 6 t o 1 f f 1 6 ( t h e s e c o d e s a r e n o t i n c l u d e d i n o s d r o m a r e a ) . b 7b 0b 7b 0 r a 6r a 5r a 4r a 3r a 2r a 1r f 8r f 7r f 6r f 5r f 4r f 3r f 2r f 1r f 0 c o l o r c o d e c h a r a c t e r c o d e 1 ( s e e n o t e 2 ) 0 o u t 2 c o n t r o l a t t r i b u t e c o d e ( s e e n o t e 1 ) b i t n a m ef u n c t i o n 69 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 (4) character color character colors are specified by ra1 to ra3 of osd ram. color data are set by color register i (co1 to co8: addresses 00e6 16 to 00e9 16 , 00ec 16 to 00ef 16 ) in advance, and 8 kinds of color regis- ter i are specified by color codes. (5) character background color character background are specified by color register i as same as character color. note : the character background is displayed in the following part: (character display area) C (character font) (border) C (button display area) accordingly, the character background color and the color signal for these sections cannot be mixed. fig. 8.10.19 color register i (i = 1 to 8) (6) out1, out2 signals out1 signal is used to erase a back ground tv image. the output waveform of out1 signal is controlled by combining the following bits; the display mode selection bits (bits 0 to 2 of the block i control register), the border type selection bit (bit 1 of the osd control regis- ter), and the out1 output control bit (bit 6 of color register i). figure 8.10.20 and 8.10.21 shows the output example of r, g, b, and out1. out2 signal is used to change the luminance of a background tv image. the output waveform of out2 signal is blank output and is controlled per character unit by ra6 of osd ram. b 7b 6b 5b 4b 3b 2b 1b 0 c o l o r r e g i s t e r i ( c o 1 t o c o 8 ) ( i = 1 t o 8 ) [ a d d r e s s e s 0 0 e 6 1 6 t o 0 0 e 9 1 6 , 0 0 e c 1 6 t o 0 0 e f 1 6 ] bn a m ef u n c t i o n s a f t e r r e s e t r w c o l o r r e g i s t e r i 0 i n d e t e r m i n a t e r w 1 g s i g n a l o u t p u t s e l e c t i o n b i t ( c o i 1 ) 0 : n o o u t p u t 1 : o u t p u t r w 2 b s i g n a l o u t p u t s e l e c t i o n b i t ( c o i 2 ) 0 : n o o u t p u t 1 : o u t p u t r w 3r s i g n a l o u t p u t ( b a c k g r o u n d ) s e l e c t i o n b i t ( c o i 3 ) 0 : n o o u t p u t 1 : o u t p u t r w 4 g s i g n a l o u t p u t ( b a c k g r o u n d ) s e l e c t i o n b i t ( c o i 4 ) 0 : n o o u t p u t 1 : o u t p u t r w 5b s i g n a l o u t p u t ( b a c k g r o u n d ) s e l e c t i o n b i t ( c o i 5 ) 0 : n o o u t p u t 1 : o u t p u t r w 6 o u t 1 o u t p u t c o n t r o l b i t ( c o i 6 ) 0 : c h a r a c t e r o u t p u t 1 : b l a n k o u t p u t r w 7 0 r @ r s i g n a l o u t p u t s e l e c t i o n b i t ( c o i 0 ) 0 : n o o u t p u t 1 : o u t p u t n o t h i n g i s a s s i n e d . t h i s b i t i s a w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . i n d e t e r m i n a t e i n d e t e r m i n a t e i n d e t e r m i n a t e i n d e t e r m i n a t e i n d e t e r m i n a t e i n d e t e r m i n a t e 70 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 fig. 8.10.20 output example of r, g, b and out1 (character color: green, character background color: blue) (in osd mode) d i s p l a y m o d e o s d c o l o r r e g i s t e r i b 6 b 5 b 4 b 3 b 2 b 1 o s d ( n o t b o r d e r e d ) 0 0 0 0 1 o s d ( b o r d e r e d ) 1 1 0 0 1 0 0 0 0 1 0 0 1 0 0 1 1 0 0 g o u t p u t = f o n t = f o n t = f o n t = f o n t o u t 1 o u t p u t = a r e a = f o n t + b o r d e r = f o n t b o u t p u t ( b a c k g r o u n d o u t p u t ) n o o u t p u t = l ( s e e n o t e 1 ) = a r e a f o n t n o o u t p u t = l ( s e e n o t e 1 ) = a r e a f o n t b o r d e r d i s p l a y e x a m p l e b 0 0 0 0 0 = a r e a n o t e s 1 : w h e n p o s i t i v e p o l a r i t y i s s e l e c t e d . 2 : e x a m p l e s o f a l l b o r d e r e d d i s p l a y a r e s h o w n . = g r e e n ( = g ) = b l u e ( = b ) = b l a c k ( = o u t 1 ) = w h i t e ( = r + g + b ) o s d m o d e c h a r a c t e r d i s p l a y a r e a ( a r e a ) b u t t o n m o d e c h a r a c t e r d i s p l a y a r e a f o n t = f o n t p a t t e r n o u t p u t a r e a = c h a r a c t e r d i s p l a y a r e a i n o s d m o d e b o r d e r = b o r d e r p a t t e r n o u t p u t a r o u n d f o n t b u t t o n = b u t t u n d i s p l a y o u t p u t a r o u n d a r e a 71 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 fig. 8.10.21 output example of r, g, b and out1 (character color: green, character background color: blue) (in button mode) b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 1 0 = f o n t + b u t t o n = f o n t + b u t t o n = f o n t + b u t t o n = a r e a + b u t t o n = f o n t + b o r d e r + b u t t o n = b u t t o n = b u t t o n = a r e a + b u t t o n f o n t 0 0 0 0 1 0 0 1 1 0 = a r e a + b u t t o n f o n t b o r d e r = a r e a + b u t t o n = f o n t + b u t t o n = f o n t + b u t t o n n o t e s 1 : w h e n p o s i t i v e p o l a r i t y i s s e l e c t e d . 2 : e x a m p l e s o f a l l b o r d e r e d d i s p l a y a r e s h o w n . 3: e x a m p l e s o f b u t t o n d i s p l a y b y r a 4 a n d r a 5 o f o s d r a m a r e s h o w n . = g r e e n ( = g ) = b l u e ( = b ) = b l a c k ( = o u t 1 ) = w h i t e ( = r + g + b ) o s d m o d e c h a r a c t e r d i s p l a y a r e a ( a r e a ) b u t t o n m o d e c h a r a c t e r d i s p l a y a r e a f o n t = f o n t p a t t e r n o u t p u t a r e a = c h a r a c t e r d i s p l a y a r e a i n o s d m o d e b o r d e r = b o r d e r p a t t e r n o u t p u t a r o u n d f o n t b u t t o n = b u t t u n d i s p l a y o u t p u t a r o u n d a r e a d i s p l a y m o d e o s d c o l o r r e g i s t e r i o s d ( n o t b o r d e r e d ) o s d ( b o r d e r e d ) g o u t p u t o u t 1 o u t p u t b o u t p u t ( b a c k g r o u n d o u t p u t ) d i s p l a y e x a m p l e 72 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 (7) attribute (block display) the attributes (border, button display, block shadow display) are controlled to the character font. the display mode is specified per block unit by bits 0 to 2 of the block i control register. the attributes to be controlled are different depending on each mode. osd mode .............. border button mode ....... border, button display, block shadow display fig. 8.10.22 border priority border the border is output in the osd and button modes. the all bordered (bordering around of character font) and the shadow bordered (bordering right and bottom sides of character font) are selected per screen unit by bit 1 of osd control register (refer to figure 8.10.4). the on/off switch for borders can be controlled per block unit by bit 2 of the block i control register (refer to fig- ure 8.10.8). the out1 signal is used for border output. the horizontal size (x) of border is 1t osc (t osc : osd oscillation cycle) regardless of the character font dot size. the vertical size (y) is 1h (2h in the bi-scan mode) regardless of character font. notes 1: the border dot area is the shaded area as shown in figure 8.10.23. 2: when the border dot overlaps on the next character font, the charac- ter font has priority (refer to figure 8.10.22 a). when the border dot overlaps on the next character back ground, the border has priority (refer to figure 8.10.22 b). 3: the border in vertical out of character area is not displayed in osd mode (refer to figure 8.10.22). c h a r a c t e r b o u n d a r y b c h a r a c t e r b o u n d a r y a c h a r a c t e r b o u n d a r y b p r i o r i t y l e v e l : b u t t o n d i s p l a y = b l o c k s h a d o w d i s p l a y > f o n t d i s p l a y > b o r d e r d i s p l a y > c h a r a c t e r b a c k g r o u n d d i s p l a y 73 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 a l l b o r d e r 1 6 d o t s 2 0 d o t s c h a r a c t e r f o n t a r e a b o r d e r f o n t s h a d o w b o r d e r b o r d e r d o t ( = 1 t o s c ) w i d t h o f b o r d e r d o t ( = 1 h ) ( s e e n o t e ) n o t e : i t i s p o s s i b l e i n o n l y b u t t o n m o d e . b o r d e r d i s p l a y a r e a t h i s i s d i s p l a y e x a m p l e w h e n 1 t o s c 5 1 h o f d o t s i z e . b o r d e r d o t ( = 1 t o s c ) w i d t h o f b o r d e r d o t ( = 1 h ) ( s e e n o t e ) fig. 8.10.23 border display example and border area 74 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 button display there are 2 kinds of displays; on button display and off button display. the button display is controlled per charac- ter unit by ra4 and ra5 of osd ram. the button display area is around the character display area in the button mode. the on/off button is displayed by outputting white (r + g + b) or black (out) to this area. the horizontal size (x) of button display area is for 2 dots re- gardless of the character font dot size. the vertical size (y) is for 2 dots regardless of the vertical dot size of character font. fig. 8.10.24 on/off button display and block shadow display a block shadow display the block shadow is displayed to the character display area in the button mode. the block shadow display is controlled per character unit by ra4 and ra5 of osd ram. figure 8.10.24 shows each display example. the button/block shadow can be displayed to the character area where combined ar- bitrary (within 24 characters for a block). set each character in this case, too. set 0 to all attribute codes between on button, off button and block shadow displays. o n b u t t o no f f b u t t o n 2 0 d o t s 1 6 d o t s b u t t o n d i s p l a y a r e a ( = 2 d o t s ) b u t t o n d i s p l a y a r e a ( = 2 d o t s ) = c h a r a c t e r f o n t d i s p l a y a r e a 1 6 d o t s 2 2 d o t s s h a d o w d i s p l a y a r e a ( = 2 d o t s ) s h a d o w d i s p l a y a r e a ( = 2 d o t s ) 75 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 fig. 8.10.25 attribute codes and display examples n o t e s 1 : w h e n r a 4 = r a 5 = 1 , s h a d o w b o r d e r c a n b e d i s p l a y e d i n c h a r a c t e r d i s p l a y a r e a . 2 : w h e n r a 4 = r a 5 = 0 , c h a r a c t e r b a c k g r o u n d c o l o r c a n b e c o l o r e d i n a l l d i s p l a y a r e a . 3 : 3 k i n d s o f d i s p l a y ( o n b u t t o n , o f f b u t t o n a n d b l o c k s h a d o w ) c a n b e d i s p l a y e d w i t h i n t h e s a m e b l o c k . b e s u r e t o s e t a t t r i b u t e s b e t w e e n t h e s e d i s p l a y t o 0 . a t t r i b u t e c o d er a 5 a t t r i b u t e c o d er a 4 = c h a r a c t e r d i s p l a y a r e a i n o s d m o d e 0 0 0 1 0 1 1 0 0 0 1 0 1 0 0 0 1 1 ( s e e n o t e s 2 , 3 )( s e e n o t e 1 ) 76 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 (8) multiline display this microcomputer can ordinarily display 2 lines on the crt screen by displaying 2 blocks at different vertical positions. in addition, it can display 3 lines or more by using osd interrupts. an osd interrupt request occurs at the point at which display of each block has been completed. in other words, when a scanning line reaches the point of the display position (specified by the block i v registers) of a certain block, the character display of that block starts, and an interrupt occurs at the point at which the scanning line ex- ceeds the block. fig. 8.10.26 note on occurence of osd interrupt notes 1: an osd interrupt does not occur at the end of display when the block is not displayed. in other words, if a block is set to off display by the display control bit of the block control register i (addresses 00f9 16 and 00fa 16 ), an osd interrupt request does not occur (refer to fig- ure 8.10.26 (a)). 2: when another block display appeares while one block is displayed, an osd interrupt request occurs only once at the end of the another block display (refer to figure 8.10.26 (b)). 3: on the screen setting window, an osd interrupt occurs even at the end of the block (off display) out of window (refer to figure 12.11.36 (c)). (b) (c) block 1 (on display) block 2 (on display) block 1' (on display) block 2' (on display) block 1 (on display) block 2 (on display) block 1' (off display) block 2' (off display) ?sd interrupt request ?sd interrupt request ?sd interrupt request ?sd interrupt request ?sd interrupt request ?sd interrupt request no ?sd interrupt request block 1 block 2 ?sd interrupt request ?sd interrupt request ?sd interrupt request ?sd interrupt request block 1 block 2 block 1' on display (osd interrupt request occurs at the end of block display) off display (osd interrupt request does not occur at the end of block display) window no ?sd interrupt request no ?sd interrupt request (a) 77 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 (9) window function the window function can be set windows on-screen, and output osd within only the area where the window is set. the on/off for vertical window function is performed by bit 4 of the osd control register. the top boundary is set by the top border con- trol register (tbr) and the bottom boundary is set by bottom border control register (bbr). the left boundary is set by the left border control register (lbr), and the right boundary is set by the right bor- der control register (rbr). the left and right boundarys can be adjusted minutely by bits 2 and 3 of the osd control register (address 00ea 16 ). note: the sprite display is not effected by the window function. fig. 8.10.27 example of window function w i n d o w fgh ij klmno pqrst b o t t o m b o u n d a r y o f w i n d o w t o p b o u n d a r y o f w i n d o w s c r e e n w i n d o w r i g h t b o u n d a r y o f w i n d o w 4 t o s c 5 r b r + 1 t o s c 5 w h 4 t o s c 5 l br + 1 t o s c 5 w h t d e f 4 h s y n c h d e f t b r b b r v s y n c l b r: v a l u e o f l e f t b o r d e r c o n t r o l r e g i s t e r r b r: v a l u e o f r i g h t b o r d e r c o n t r o l r e g i s t e r w h : v a l u e ( 0 t o 3 ) o f w i n d o w h o r i z o n t a l p o s i t i o n m i n u t e a d j u s t m e n t b i t t o s c : o s d o s c i l l a t i o n c y c l e t d e f 4 : 4 t o s c t b r: v a l u e o f t o p b o r d e r c o n t r o l r e g i s t e r b b r: v a l u e o f b o t t o m b o r d e r c o n t r o l r e g i s t e r h d e f : 1 7 h h: h s y n c l e f t b o u n d a r y o f w i n d o w 78 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 fig. 8.10.29 bottom border control register fig. 8.10.28 top border control register b 7b 6b 5b 4b 3b 2b 1b 0 t o p b o r d e r c o n t r o l r e g i s t e r ( t b r ) [ a d d r e s s 0 2 4 5 1 6 ] bn a m ef u n c t i o n s a f t e r r e s e t rw t o p b o r d e r c o n t r o l r e g i s t e r 0 t o 7 c o n t r o l b i t s o f t o p b o r d e r ( t b r 0 t o t b r 7 ) t o p b o r d e r p o s i t i o n = h d e f + h 5 n ( n : s e t t i n g v a l u e , h d e f : 1 7 h , h : h s y n c ) i n d e t e r m i n a t e rw n o t e s 1 : s e t v a l u e s e x c e p t 0 0 1 6 t o t b r . 2 : s e t v a l u e s f i t f o r t b r b b r . b 7b 6b 5b 4b 3b 2b 1b 0 b o t t o m b o r d e r c o n t r o l r e g i s t e r ( b b r ) [ a d d r e s s 0 2 4 6 1 6 ] bn a m ef u n c t i o n sa f t e r r e s e trw b o t t o m b o r d e r c o n t r o l r e g i s t e r 0 t o 7 c o n t r o l b i t s o f b o t t o m b o r d e r ( b b r 0 t o b b r 7 ) i n d e t e r m i n a t e rw b o t t o m b o r d e r p o s i t i o n = h d e f + h 5 n ( n : s e t t i n g v a l u e , h d e f : 1 7 h , h : h s y n c ) n o t e s 1 : s e t v a l u e s e x c e p t 0 0 1 6 t o b b r . 2 : s e t v a l u e s f i t f o r t b r b b r . 79 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 fig. 8.10.30 left bordercontrol register fig. 8.10.31 right border control register b 7b 6b 5b 4b 3b 2b 1b 0 l e f t b o r d e r c o n t r o l r e g i s t e r ( l b r ) [ a d d r e s s 0 2 4 0 1 6 ] bn a m ef u n c t i o n s l e f t b o r d e r c o n t r o l r e g i s t e r c o n t r o l b i t s o f l e f t b o r d e r ( l b r 0 t o l b r 6 ) 0 t o 6 l e f t b o r d e r p o s i t i o n = t d e f 4 + 4 t o s c 5 n + 1 t o s c 5 w h ( n : s e t t i n g v a l u e , t d e f 4 : 4 t o s c , t o s c : o s d o s c i l l a t i o n c y c l e , w h : v a l u e ( 0 t o 3 ) o f w i n d o w h o r i z o n t a l p o s i t i o n m i n u t e a d j u s t m e n t b i t ) n o t h i n g i s a s s i g n e d . t h i s b i t i s w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s i n d e t e r m i n a t e . 7 a f t e r r e s e t r w 0 rw 0r n o t e : s e t v a l u e s f i t f o r l b r r b r . b 7b 6b 5b 4b 3b 2b 1b 0 r i g h t b o r d e r c o n t r o l r e g i s t e r ( r b r ) [ a d d r e s s 0 2 4 1 1 6 ] bn a m ef u n c t i o n s r i g h t b o r d e r c o n t r o l r e g i s t e r c o n t r o l b i t s o f l e f t b o r d e r ( r b r 0 t o r b r 6 ) 0 t o 6 n o t h i n g i s a s s i g n e d . t h i s b i t i s w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s i n d e t e r m i n a t e . 7 a f t e r r e s e t r w 0 rw 0r n o t e : s e t v a l u e s f i t f o r l b r r b r . r i g h t b o r d e r p o s i t i o n = t d e f 4 + 4 t o s c 5 n + 1 t o s c 5 w h ( n : s e t t i n g v a l u e , t d e f 4 : 4 t o s c , t o s c : o s d o s c i l l a t i o n c y c l e , w h : v a l u e ( 0 t o 3 ) o f w i n d o w h o r i z o n t a l p o s i t i o n m i n u t e a d j u s t m e n t b i t ) 80 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 8.10.2 sprite display this is especially suitable for cursor and other displays as its func- tion allows for display in any position, regardless of the validity of other osds or display positions. each sprite font is rom font con- sisting of 16 horizontal dots 5 20 vertical dots, and there are 4 kinds. when sprite display overlaps with other osds, sprite display is always given priority. fig. 8.10.32 sprite display example b r i g h t n e s s t i n t s o u n d m o n a u r a l s t e r e o u s e r s e l e c t s p r i t e d i s p l a y s p r i t e f o n t 1 s p r i t e f o n t 2 n o t e : s p r i t e f o n t s 1 a n d 2 a r e d i s p l a y e d b y s y n t h e s i z i n g . s y n t h e s i s s p r i t e f o n t s 1 a n d 2 ( p e r s p r i t e f o n t u n i t ) k i n d s o f c h a r a c t e r s i z e s d o t s i z e c h a r a c t e r f o n t c o l o r i n g n o t e s 1 : i t i s p o s s i b l e t o s e t i n a n y p o s i t i o n r e g a r d l e s s o f v e r t i c a l d i s p l a y p o s i t i o n s o f t h e b l o c k d i s p l a y . t h e v e r t i c a l d i s p l a y s t a r t p o s i t i o n s o f t h e s p r i t e d i s p l a y i s t h e s a m e a s t h a t o f t h e b l o c k d i s p l a y . 2 : i t i s p o s s i b l e t o s e t i n a n y p o s i t i o n r e g a r d l e s s o f h o r i z o n t a l d i s p l a y p o s i t i o n o f b l o c k d i s p l a y . 3 : i t i s t h e s a m e d i s p l a y a r e a a s o s d m o d e ( r e f e r t o f i g u r e 8 . 1 0 . 3 ) . 4 : a s f o r c h a r a c t e r f o n t d a t a s t o r i n g a d d r e s s r e f e r t o 8 . 1 0 . 1 b l o c k d i s p l a y ( 3 ) m e m o r y f o r o s d . t h e c h a r a c t e r s o f c h a r a c t e r c o d e s f 8 1 6 t o f f 1 6 c a n b e a l s o u s e d f o r t h e b l o c k d i s p l a y . 5 : r e f e r t o 8 . 1 0 . 1 b l o c k d i s p l a y ( 2 ) d o t s i z e . t h e d o t s i z e i n t h e b i - s c a n m o d e i s 1 t o s c 5 2 h . 6 : r e f e r t o 8 . 1 0 . 1 b l o c k d i s p l a y ( 4 ) c h a r a c t e r c o l o r . o n l y c o l o r r e g i s t e r s 1 t o 4 c a n b e s p e c i f i e d . 7 : h = h s y n c 8 : t o s c = o s d o s c i l l a t i o n c y c l e f e a t u r e s p a r a m e t e r n u m b e r o f d i s p l a y c h a r a c t e r s 1 c h a r a c t e r s 5 1 l i n e ( d i s p l a y b y s y n t h e s i z i n g 2 k i n d s o f c h a r a c t e r s ) d o t s t r u c t u r e k i n d s o f c h a r a c t e r s 4 k i n d s ( c h a r a c t e r c o d e = f 8 1 6 t o f f 1 6 ) ( s e e n o t e 4 ) 1 k i n d 1 t o s c 5 1 h ( s e e n o t e s 5 , 7 , 8 ) 1 6 5 2 0 d o t s ( s e e n o t e 3 ) o t h e r fu n c t i o n sc o r r e s p o n d i n g t o b i - s c a n o s d o u t p u t r , g , b d i s p l a y p o s i t i o nh o r i z o n t a l : 2 5 3 l e v e l s ( s e e n o t e 2 ) , v e r t i c a l : 2 5 5 l e v e l s ( s e e n o t e 1 ) table 8.10.4 features of sprite display to display sprite font, osd rom font data for 2 characters is used. these 2 fonts can be colored with any color and can be displayed by synthesizing as a character. the features and display example of sprite display are shown below. notes 1: the sprite display is not effected by the window function. 2: the sprite display cannot output character background color or out2. 81 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 fig. 8.10.33 sprite h register fig. 8.10.35 sprite v register b 7b 6b 5b 4b 3b 2b 1b 0 s p r i t e h r e g i s t e r ( s h p ) [ a d d r e s s 0 0 e 4 1 6 ] bn a m ef u n c t i o n s s p r i t e h r e g i s t e r 0 t o 7 h o r i z o n t a l d i s p l a y s t a r t p o s i t i o n c o n t r o l b i t s o f s p r i t e o s d ( s h p 0 t o s h p 7 ) h o r i z o n t a l d i s p l a y s t a r t p o s i t i o n = t d e f 2 + 2 t o s c n ( n : s e t t i n g v a l u e , t d e f 2 : 2 t o s c , t o s c : o s d o s c i l l a t i o n c y c l e ) a f t e r r e s e trw rw 0 n o t e s 1 : s e t v a l u e s e x c e p t 0 0 1 6 t o 0 2 1 6 t o s h p . 2 : w h e n s e l e c t i n g r a s t e r p a t t e r n i n g d i s p l a y , s e t t i n g v a l u e i s s y n c h r o n i z e d w i t h v s y n c s i g n a l ; w h e n s e l e c t i n g s p r i t e d i s p l a y , i t i s n o t s y n c h r o n i z e d . 5 b 7b 6b 5b 4b 3b 2b 1b 0 s p r i t e v r e g i s t e r ( s v p ) [ a d d r e s s 0 0 e 5 1 6 ] bn a m ef u n c t i o n s s p r i t e v r e g i s t e r 0 t o 7 h o r i z o n t a l d i s p l a y s t a r t p o s i t i o n c o n t r o l b i t s o f s p r i t e o s d ( s v p 0 t o s v p 7 ) ( s e e n o t e 1 ) h o r i z o n t a l d i s p l a y s t a r t p o s i t i o n = h d e f + h 5 n ( n : s e t t i n g v a l u e , h d e f : 1 7 h , h : h s y n c ) n o t e : s e t v a l u e s e x c e p t 0 0 1 6 t o t h e s v p . a f t e r r e s e trw rw i n d e t e r m i n a t e fig. 8.10.34 note on horizontal display start position of sprite display n h ': v a l u e o f s p r i t e h r e g i s t e r ( d e c i m a l ) ( s e e n o t e ) t o s c : o s d o s c i l l a t i o n c y c l e t d e f 2 : 2 t o s c n o t e : d o n o t s e t 0 t o 2 t o n h ' . h s y n c 2t o s c 5 n h ' t d e f 2 w h e n s e t t i n g t h e s p r i t e h r e g i s t e r t o 0 3 1 6 , t h e i n t e r v a l o f t d e f 2 + 2 t o s c 5 3 = 8 t o s c i s n e c e s s a r y f r o m a r i s i n g e d g e ( n e g a t i v e p o l a r i t y ) t o h o r i z o n t a l d i s p l a y s t a r t p o s i t i o n . 82 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 fig. 8.10.35 sprite control register b 7b 6b 5b 4b 3b 2b 1b 0 s p r i t e c o n t r o l r e g i s t e r ( s c ) [ a d d r e s s 0 0 e 3 1 6 ] bn a m ef u n c t i o n s a f t e r r e s e t r w s p r i t e c o n t r o l r e g i s t e r 0 , 1 4 , 5 s p r i t e f o n t 1 c o l o r r e g i s t e r s p e c i f i c a t i o n b i t ( s c 0 , s c 1 ) 0 0 w r w r n o t e : t h i s b i t i s v a l i d w h e n b i t 0 o f t h e o s d c o n t r o l r e g i s t e r t o 1 . 2 , 3 s p r i t e f o n t 2 c o l o r r e g i s t e r s p e c i f i c a t i o n b i t ( s c 2 , s c 3 ) 0w r 6 , 7 s p r i t e / r a s t e r p a t t e r n i n g c o n t r o l b i t ( s c 6 , s c 7 ) ( s e e n o t e ) 0w r s p r i t e f o n t s e l e c t i o n b i t ( s c 4 , s c 5 ) s c 5 s c 4 c h a r a c t e r c o d e s p r i t e 1s p r i t e 2 0 0 1 1 0 1 0 1 f 8 1 6 f a 1 6 f c 1 6 f e 1 6 f 9 1 6 f b 1 6 f d 1 6 f f 1 6 s c 1 @ s c 0 00 : c o l o r r e g i s t e r 1 01 : c o l o r r e g i s t e r 2 10 : c o l o r r e g i s t e r 3 11 : c o l o r r e g i s t e r 4 s c 3 @ s c 2 00 : c o l o r r e g i s t e r 1 01 : c o l o r r e g i s t e r 2 10 : c o l o r r e g i s t e r 3 11 : c o l o r r e g i s t e r 4 s c 7 @ s c 6 00 : d i s p l a y o f f 01 : d o n o t s e t 10 : s p r i t e d i s p l a y 11 : r a s t e r p a t t e r n i n g d i s p l a y 83 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 8.10.3 raster display the raster display is displayed on the lower layer than the sprite and block layers. there are 2 kinds of displays; the flat display and the patterning display. in the raster flat display, an entire screen (raster) can be colored by setting the following bits; bits 5 to 7 of the osd i/o polarity register and bits 6 and 7 of the osd control register. since each of the r, g, b, out1, and out2 pins can be switched to raster coloring output, 8 raster colors can be obtained. in the raster patterning display, sprite fonts are displayed repeat- edly on an entire screen (raster). at this time, set 1 to bits 6 and 7 of the sprite control register. horizontal display start positions of the raster patterning display are set by the sprite h register. at this time, setting value is synchro- nized with v sync signal. characters for patterning are set by bits 4 and 5 of the sprite con- trol register and coloring are set by bits 0 to 3. the raster color is output on the background of sprite font. fig. 8.10.36 raster flat display example note that the raster patterning display and the sprite display can- not be used at the same time. when the character color/the character background color overlaps with the raster color, the color (r, g, b, out1, out2), specified for the character color/the character background color, takes priority of the raster color. this ensures that the character color/the character background color is not mixed with the raster color. the raster flat display example is shown in figure 8.10.36, the raster patterning display example is shown in figure 8.10.37. h s y n c a ' a o u t 1 r g b : c h a r a c t e r c o l o r r e d ( r + o u t 1 + o u t 2 ) : b o r d e r c o l o r b l a c k ( o u t 1 + o u t 2 ) : b a c k g r o u n d c o l o r m a g e n t a ( r + b + o u t 1 + o u t 2 ) : r a s t e r c o l o r b l u e ( r + o u t 1 + o u t 2 ) s i g n a l s a c r o s s a - a ' o u t 2 84 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 fig. 8.10.37 raster patterning display example h s y n c t d e f 2 2 t o s c ~ n h ' s c r e e n s p r i t e f o n t r a s t e r c o l o r b l u e ( b + o u t 1 ) s p r i t e f o n t 1 c o l o r b l a c k ( o u t 1 ) s p r i t e f o n t 2 c o l o r w h i t e ( r + g + b + o u t 1 ) ( s e e n o t e ) n o t e : d o n o t s e t 0 t o 2 t o n h ' . n h ': v a l u e o f s p r i t e h r e g i s t e r ( d e c i m a l ) ( s e e n o t e ) t o s c : o s d o s c i l l a t i o n c y c l e t d e f 2 : 2 t o s c w h e n s e t t i n g 0 3 1 6 t o s p r i t e h r e g i s t e r , i t i s n e e d t d e f 2 + 2 t o s c 5 3 = 8 t o s c i n t e r v a l s f r o m a r i s i n g e d g e ( n e g a t i v e p o l a r i t y ) o f h s y n c s i g n a l t o a h o r i z o n t a l d i s p l a y s t a r t p o s i t i o n . 85 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 ad h , ad l 01,s? 01,s? pc h pc l ps ad h ad l pc ? ? : undefined instruction decode ? undefined instruction decoding signal occurs.internal reset signal occurs. f sync address data reset sequence 01,s fffe 16 ffff 16 : invalid : program counter s : stack pointer pc ad l , ad h : jump destination address of reset fig.8.11.1 sequence at detecting software runaway detection 8.11 software runaway detect function this microcomputer has a function to decode undefined instructions to detect a software runaway. when an undefined op-code is input to the cpu as an instruction code during operation, the following processing is done. the cpu generates an undefined instruction decoding signal. the device is internally reset because of occurrence of the unde- fined instruction decoding signal. a as a result of internal reset, the same reset processing as in the case of ordinary reset operation is done, and the program restarts from the reset vector. note, however, that the software runaway detecting function cannot be invalid. 86 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 8.12. reset circuit when the oscillation of a quartz-crystal oscillator or a ceramic reso- nator is stable and the power source voltage is 5 v 10 %, hold the reset pin at low for 2 m s or more, then return is to high. then, as shown in figure 8.12.2, reset is released and the program starts form the address formed by using the content of address ffff 16 as the high-order address and the content of the address fffe 16 as the low-order address. the internal state of microcomputer at reset are shown in figures 8.2.3 to 8.2.6. an example of the reset circuit is shown in figure 8.12.1. the reset input voltage must be kept 0.9 v or less until the power source voltage surpasses 4.5 v. fig.8.12.2 reset sequence fig.8.12.1 example of reset circuit power source voltage 0 v reset input voltage 0 v 4.5 v 0.9 v poweron vcc reset vss microcomputer 1 5 4 3 0.1 m f m51953al x in f reset internal reset sync address data 32768 count of x in clock cycle (see note 3) reset address from the vector table ? ? 01, s 01, s-1 01, s-2 fffe ffff ad h , ad l ? ? ? ? ? ad l ad h notes 1 : f(x in ) and f( f ) are in the relation : f(x in ) = 2? ( f ). 2 : a question mark (?) indicates an undefined state that depends on the previous state. 3 : immediately after a reset, timer 3 and timer 4 are connected by hardware. at this time, ?f 16 ?is set in timer 3 and ?7 16 ?is set to timer 4. timer 3 counts down with f(x in )/16, and reset state is released by the timer 4 overflow signal. 87 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 8.13 clock generating circuit the built-in clock generating circuit is shown in figure 8.13.3. when the stp instruction is executed, the internal clock f stops at high. at the same time, timers 3 and 4 are connected by hardware and ff 16 is set in timer 3 and 07 16 is set in the timer 4. select f(x in )/16 as the timer 3 count source (set bit 0 of the timer mode register 2 to 0 before the execution of the stp instruction). moreover, set the timer 3 and timer 4 interrupt enable bits to disabled (0) before ex- ecution of the stp instruction). the oscillator restarts when external interrupt is accepted. however, the internal clock f keeps its high until timer 4 overflows, allowing time for oscillation stabilization when a ceramic resonator or a quartz-crystal oscillator is used. when the wit instruction is executed, the internal clock f stops in the high but the oscillator continues running. this wait state is re- leased when an interrupt is accepted (see note). since the oscillator does not stop, the next instruction can be executed at once. when returning from the stop or the wait state, to accept an interrupt, set the corresponding interrupt enable bit to 1 before executing the stp or the wit instructions. note: in the wait mode, the following interrupts are invalid. ? v sync interrupt ? osd interrupt ? timer 2 interrupt using external clock input from tim2 pin as count source ? timer 3 interrupt using external clock input from tim3 pin as count source ? timer 4 interrupt using f(x in )/2 as count source ? timer 1 interrupt using f(x in )/4096 as count source ? f(x in )/4096 interrupt ? multi-master i 2 c-bus interface interrupt ? a-d conversion interrupt ? sprite interrupt a circuit example using a ceramic resonator (or a quartz-crystal os- cillator) is shown in figure 8.13.1. use the circuit constants in accor- dance with the resonator manufactures recommended values. a cir- cuit example with external clock input is shown in figure 8.13.2. in- put the clock to the x in pin, and open the x out pin. fig.8.13.1 ceramic resonator circuit example fig.8.13.2 external clock input circuit example x in x out c in microcomputer c out x in microcomputer vcc vss external oscillation circuit fig.8.13.3 clock generating circuit block diagram interrupt request interrupt disable flag i reset sq r stp instruction sq r wit instruction s q r stp instruction reset internal clock f 1/2 1/8 timer 3 timer 4 x out x in tm20 tm22 selection gate : connected to black side at reset. tm2 : timer mode register 2 88 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 reset vss vcc circuit example 1 reset vss vcc circuit example 2 note : make the level change from ??to ??at the point at which the power source voltage exceeds the specified voltage. 8.14 display oscillation circuit the osd oscillation circuit has a built-in clock oscillation circuits, so that a clock for osd can be obtained simply by connecting an lc, a ceramic resonator, or a quartz-crystal oscillator across the pins osc1 and osc2. which of the sub-clock or the osd oscillation circuit is selected by setting bits 0 and 1 of the interrupt input polarity register (address 00cd 16 ). 8.16 addressing mode the memory access is reinforced with 17 kinds of addressing modes. refer to series 740 89 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 power source voltage v cc input voltage cnv ss input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 5 , osc1, x in , p5 0 , p5 1 , ______ reset output voltage p0 6 , p0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 2 , p3 5 , p5 2 Cp5 5 , x out , osc2 output voltage p0 0 Cp0 5 circuit current p5 2 Cp5 5 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1 , p3 5 circuit current p5 2 Cp5 5 , p0 6 , p0 7 , p1 0 , p1 5 Cp1 7 , p2 0 Cp2 3 , p3 0 Cp3 2 , p3 5 circuit current p1 1 Cp1 4 circuit current p0 0 Cp0 5 circuit current p2 4 , p2 7 power dissipation operating temperature storage temperature symbol v cc , av cc v i v i v o v o i oh i ol1 i ol2 i ol3 i ol4 p d t opr t stg 10. absolute maximum ratings conditions all voltages are based on v ss . output transistors are cut off. parametear t a = 25 c unit v v v v v ma ma ma ma ma mw c c ratings C0.3 to 6 C0.3 to 6 C0.3 to v cc + 0.3 C0.3 to v cc + 0.3 C0.3 to 13 0 to 1 (see note 1) 0 to 2 (see note 2) 0 to 6 (see note 2) 0 to 1 (see note 2) 0 to 10 (see note 3) 550 C10 to 70 C40 to 125 power source voltage (see note 4), during cpu, osd, data slicer operation power source voltage high input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 5, s in , s clk , p5 0 , p5 1 , reset, x in , osc1, tim2, tim3, int1Cint3 high input voltage scl1, scl2, sda1, sda2 low input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 5 low input voltage scl1, scl2, sda1, sda2 low input voltage (see note 6) p5 0 , p5 1 , reset, tim2, tim3, int1Cint3, x in , osc1, s in , s clk high average output current (see note 1) p5 2 Cp5 5 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 , p3 1, p3 5 low average output current (see note 2) p5 2 Cp5 5 , p0 6 , p0 7 , p1 0 , p1 5 Cp1 7 , p3 0 Cp3 2 , p3 5 low average output current (see note 2) p1 1 Cp1 4 low average output current (see note 2) p0 0 Cp0 5 low average output current (see note 3) p2 4 Cp2 7 oscillation frequency (for cpu operation) (see note 5) x in oscillation frequency (for osd) osc1 input frequency tim2, tim3 input frequency s clk input frequency scl1, scl2 limits min. 4.5 0 0.8v cc 0.7v cc 0 0 0 7.9 5.0 5.0 7.9 typ. 5.0 0 8.0 8.0 8.0 8.0 max. 5.5 0 v cc v cc 0.4 v cc 0.3 v cc 0.2 v cc 1 2 6 1 10 8.1 9.0 17.0 8.1 100 1 400 v v v v v v v ma ma ma ma ma mhz mhz khz mhz mhz 11. recommended operating conditions (t a = C10 c to 70 c, v cc = 5 v 10 %, unless otherwise noted) v cc v ss v ih1 v ih2 v il1 v il2 v il3 i oh i ol1 i ol2 i ol3 i ol4 f(x in ) fosc f hs1 f hs2 f hs3 symbol parameter unit rc oscillating mode lc oscillating mode ceramic oscillating mode 90 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 power source current high output voltage p5 2 Cp5 5 , p1 0 Cp1 7 , p2 0 Cp2 7 ,p3 0 , p3 1 , p3 5 low output voltage p5 2 Cp5 5 , p0 0 Cp0 7 , p1 0 , p1 5 Cp1 7 , p2 0 Cp2 3 , p3 0 Cp3 2 , p3 5 low output voltage p2 4 Cp2 7 low output voltage p1 1 Cp1 4 hysteresis (see note 6) ____________ reset, p5 0 , p5 1 , tim2, tim3, int1Cint3, scl1, scl2, sda1, sda2, s in , s clk high input leak current ____________ reset , p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 5 , p5 0 , p5 1 low input leak current ____________ reset , p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 5 , p5 0 , p5 1 high input leak current p0 0 Cp0 5 i 2 c-busbus switch connection resistor (between scl1 and scl2, sda1 and sda2) max. 40 60 300 0.4 3.0 0.4 0.6 1.3 5 5 10 130 limits min. 2.4 12. electric characteristics (v cc = 5 v 10 %, v ss = 0 v, f(x in ) = 8 mhz, t a = C10 c to 70 c, unless otherwise noted) i cc v oh v ol v t+ C v tC i izh i izl i ozh r bs typ. 20 30 0.5 symbol parameter test conditions unit system operation stop mode v cc = 5.5 v, f(x in ) = 0 v cc = 4.5 v i oh = C0.5 ma v cc = 4.5 v i ol = 0.5 ma v cc = 4.5 v i ol = 10.0 ma v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v v i = 5.5 v v cc = 5.5 v v i = 0 v v cc = 5.5 v v i = 12 v v cc = 4.5 v osd off osd on test circuit v cc = 5.5 v, f(x in ) = 8 mhz ma ma v v v m a m a m a w 1 4 2 3 5 6 notes 1: the total current that flows out of the ic must be 20 ma or less. 2: the total input current to ic (i ol1 + i ol2 + i ol3 ) must be 30 ma or less. 3: the total average input current for ports p2 4 Cp2 7 to ic must be 20 ma or less. 4: connect 0.1 m f or more capacitor externally between the power source pins v cc Cv ss so as to reduce power source noise. also connect 0.1 m f or more capacitor externally between the pins v cc Ccnv ss . 5: use a quartz-crystal oscillator or a ceramic resonator for the cpu oscillation circuit. when using the data slicer, use 8 mhz. 6: p0 6 , p0 7 , p1 5 , p2 3 , p2 4 have the hysteresis when these pins are used as interrupt input pins or timer input pins. p1 1 Cp1 4 have the hysteresis when these pins are used as multi-master i 2 c-bus interface ports. p2 0 Cp2 2 have the hysteresis when these pins are used as serial i/o pins. 7: pin names in each parameter is described as below. (1) dedicated pins: dedicated pin names. (2) duble-/triple-function ports ? when the same limits: i/o port name. ? when the limits of functins except ports are different from i/o port limits: function pin name. i ol = 3 ma i ol = 6 ma 91 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 fig.12.1 measure circuits 1 3 5 2 4 6 v s s v c c v v o h o r v o l i o h o r i o l 4 . 5 v e a c h o u t p u t p i n a f t e r s e t t i n g e a c h o u t p u t p i n t o h i g h l e v e l w h e n m e a s u r i n g v o h a n d t o l o w l e v e l w h e n m e a s u r i n g v o l , e a c h p i n i s m e a s u r e d . v s s v c c 5 . 0 v e a c h i n p u t p i n v s s v c c v b s 4 . 5 v s c l 1 o r s d a 1 i b s a r b s = v b s / i b s s c l 2 o r s d a 2 r b s v s s v c c 5 . 5 v e a c h i n p u t p i n a i i z h o r i i z l v s s v c c 5 . 5 v a e a c h o u t p u t p i n a f t e r s e t t i n g e a c h o u t p u t p i n o f f s t a t e , e a c h p i n i s m e a s u r e d i oz h 1 2 v a v s s v c c x i n x o u t o s c 1 o s c 2 i c c 8 . 0 0 m h z + p o w e r s o u r c e v o l t a g e p i n v c c i s m a d e t h e o p e r a t i o n s t a t e a n d i s m e a s u r e d t h e c u r r e n t , w i t h a c e r a m i c r e s o n a t o r . 92 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 13. a-d converter characteristics (v cc = 5 v 10 %, v ss = 0 v, f(x in ) = 8 mhz, t a = C10 c to 70 c, unless otherwise noted) resolution absolute accuracy (excludig guantization error) conversion time ladder resistor analog input voltage max. 8 2.5 12.5 v ref bits lsb m s k w v min. 12.25 0 limits unit test conditions parameter symbol t conv r ladder v ia vcc = 5 v typ. 25 14. multi-master i 2 c-bus bus line characteristics bus free time hold time for start condition low period of scl clock rising time of both scl and sda signals data hold time high period of scl clock falling time of both scl and sda signals data set-up time set-up time for repeated start condition set-up time for stop condition t buf t hd; sta t low t r t hd; dat t high t f t su; dat t su; sta t su; sto max. 1000 300 min. 1.3 0.6 1.3 20+0.1c b 0 0.6 20+0.1c b 100 0.6 0.6 max. 300 0.9 300 m s m s m s ns m s m s ns ns m s m s unit standard clock mode high-speed clock mode parameter symbol note: c b = total capacitance of 1 bus line fig.14.1 definition diagram of timing on multi-master i 2 c-bus min. 4.7 4.0 4.7 0 4.0 250 4.7 4.0 sda scl p t buf s t hd ; sta t low t r t hd ; dat t high t f t su ; dat t su ; sta sr p t su ; sto t hd ; sta s sr p : start condition : restart condition : stop condition 93 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 15. prom programming method the built-in prom of the one time prom version (blank) and the built-in eprom version can be read or programmed with a general- purpose prom programmer using a special programming adapter. product m37225ecsp name of programming adapter pca7408 the prom of the one time prom version (blank) is not tested or screened in the assembly process nor any following processes. to ensure proper operation after programming, the procedure shown in figure 15.1 is recommended to verify programming. fig. 15.1 programming and testing of one time prom version programming with prom programmer screening (caution) (150? for 40 hours) verification with prom programmer functional check in target device caution : the screening temperature is far higher than the storage temperature. never expose to 150? exceeding 100 hours. 94 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 16. data required for mask orders the following are necessary when ordering a mask rom produc- tion: ? mask rom order confirmation form ? mark specification form ? data to be written to rom, in eprom form (32-pin dip type 27c101, three identical copies) or fdk gzzCsh53C91b < 88a0 > 740 family mask rom confirmation form single-chip microcomputer M37225M6-XXXSP mitsubishi electric mask rom number receipt date: section head signature supervisor signature ] customer company name tel ( ) date : date issued issuance signature note : please fill in all items marked ] . submitted by supervisor ] 1. confirmation three eproms are required for each pattern if this order is performed by eproms. one floppy disk is required for each pattern if this order is performed by a floppy disk. ordering by eproms if at least two of the three sets of eproms submitted contain identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms. checksum code for entire eprom (hexadecimal notation) eprom type (indicate the type used) (1) set ff 16 in the shaded area. 1/3 eprom address product nameascii code: 'm37225m6-' 2 7 c 1 0 1 program rom 24k bytes 00000 16 1234567890123456 1 23456789012345 6 1234567890123456 1234567890123456 1234567890123456 1234567890123456 1234567890123456 osd rom 1 osd rom 2 1234567890123456 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1234567890123456 0000f 16 0a000 16 0ffff 16 11400 16 13bff 16 15400 16 17aff 16 17b00 16 1ffff 16 17. mask confirmation form 95 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.1 96 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 m = 1 6 4d 1 6 3 = 3 3 1 6 7 = 37 1 6 2 = 3 2 1 6 2 = 32 1 6 5 = 35 1 6 m = 4d 1 6 6 = 36 0 0 0 0 0 1 6 0 0 0 0 1 1 6 0 0 0 0 2 1 6 0 0 0 0 3 1 6 0 0 0 0 4 1 6 0 0 0 0 5 1 6 0 0 0 0 6 1 6 0 0 0 0 7 1 6 a d d r e s s = 1 6 2d 1 6 ff 1 6 ff 1 6 ff 1 6 ff 1 6 ff 1 6 ff 1 6 ff 0 0 0 0 8 1 6 0 0 0 0 9 1 6 0 0 0 0 a 1 6 0 0 0 0 b 1 6 0 0 0 0 c 1 6 0 0 0 0 d 1 6 0 0 0 0 e 1 6 0 0 0 0 f 1 6 a d d r e s s a d d r e s s e s 0 0 0 0 0 1 6 t o 0 0 0 0 f 1 6 s t o r e t h e p r o d u c t n a m e . a s c i i c o d e s m 3 7 2 2 5 m 6 - a r e l i s t e d o n t h e r i g h t . t h e a d d r e s s e s a n d d a t a a r e i n h e x a d e c i m a l n o t a t i o n . a d d r e s s a n d d a t a a r e d e s c r i b e d i n h e x a d e c i m a l n o t a t i o n . i f t h e n a m e o f t h e p r o d u c t c o n t a i n e d i n t h e e p r o m s d o e s n o t m a t c h t h e n a m e o n t h e m a s k r o m c o n f i r m a t i o n f o r m , t h e r o m p r o c e s s i n g i s d i s a b l e d . p l e a s e m a k e s u r e t h e d a t a i s w r i t t e n c o r r e c t l y . g z z s h 5 3 9 1 b < 8 8 a 0 > 7 4 0 f a m i l y m a s k r o m c o n f i r m a t i o n f o r m s i n g l e - c h i p m i c r o c o m p u t e r m 3 7 2 2 5 m 6 - x x x s p m i t s u b i s h i e l e c t r i c w r i t e t h e a s c i i c o d e s t h a t i n d i c a t e t h e p r o d u c t n a m e o f m 3 7 2 2 5 m 6 t o a d d r e s s e s 0 0 0 0 0 1 6 t o 0 0 0 0 f 1 6 . ( 2 ) n o t e : ] 2 . m a r k s p e c i f i c a t i o n m a r k s p e c i f i c a t i o n m u s t b e s u b m i t t e d u s i n g t h e c o r r e c t f o r m f o r t h e t y p e o f p a c k a g e b e i n g o r d e r e d . f i l l t h e a p p r o p r i a t e m a r k s p e c i f i c a t i o n f o r m ( 4 2 p 4 b f o r m 3 7 2 2 5 m 6 - x x x s p ) a n d a t t a c h t o t h e m a s k r o m c o n f i r m a t i o n f o r m . (2/3) 3/3 gzzCsh53C91b < 88a0 > 740 family mask rom confirmation form single-chip microcomputer M37225M6-XXXSP mitsubishi electric inputting the character rom e x a m p l e ) t h e f o n t d a t a 6 0 ( s h a d e d a r e a ) o f t h e c h a r a c t e r c o d e 0 a a 1 6 i s s t o r e d i n a d d r e s s 1 0 0 1 0 0 1 0 1 0 1 0 1 0 1 0 0 2 = 1 2 5 5 4 1 6 . 0 a 1 6 0 b 1 6 0 c 1 6 0 d 1 6 0 e 1 6 0 f 1 6 1 0 1 6 1 1 1 6 1 2 1 6 1 3 1 6 1 4 1 6 1 5 1 6 1 6 1 6 1 7 1 6 1 8 1 6 1 9 1 6 1 a 1 6 1 b 1 6 1 c 1 6 1 d 1 6 d b 7d b 6d b 5d b 4d b 3d b 2d b 1d b 0d b 7d b 6d b 5d b 4d b 3d b 2d b 1d b 0 l e f t a r e ar i g h t a r e a l i n e n u m b e r c h a r a c t e r c o d e 0 a a 1 6 l i n e n u m b e r n o t e : t h e 1 2 0 - b y t e a d d r e s s e s c o r r e s p o n d i n g t o t h e c h a r a c t e r c o d e s 0 7 f 1 6 , 0 8 0 1 6 a n d 1 f 1 6 i n o s d r o m a r e t h e t e s t d a t a s t o r n i n g a r e a . s e t f f 1 6 t o t h e a r e a ( w e s t o r e s t h e t e s t d a t a t o t h i s a r e a a n d t h e d i f f e r e n t d a t a f r o m f f 1 6 i s s t o r e d f o r t h e a c t u a l p r o d u c t s . ) t h e t e s t d a t a s t o r i n g a r e a : a d d r e s s e s 1 1 0 0 0 1 6 + ( 4 + 2 n ) 5 1 0 0 1 6 + f e 1 6 t o 1 1 0 0 0 1 6 + ( 5 + 2 n ) 5 1 0 0 1 6 + 0 1 1 6 ( n = 0 t o 1 9 ) a d d r e s s e s 1 5 0 0 0 1 6 + ( 4 + 2 n ) 5 1 0 0 1 6 + f e 1 6 a n d 1 5 0 0 0 1 6 + ( 4 + 2 n ) 5 1 0 0 1 6 + f f 1 6 ( n = 0 t o 1 9 ) t h e 5 1 2 0 - b y t e a d d r e s s e s c o r r e s p o n d i n g t o t h e c h a r a c t e r c o d e s 1 8 0 1 6 t o 1 f f 1 6 a r e n o t i n o s d r o m . s e t f f 1 6 t o t h e a r e a , t o o . a d d r e s s e s 1 5 0 0 0 1 6 + ( 5 + 2 n ) 5 1 0 0 1 6 + 0 0 1 6 t o 1 5 0 0 0 1 6 + ( 5 + 2 n ) 5 1 0 0 1 6 + f f 1 6 ( n = 0 t o 1 9 ) a d d r e s s e s 1 5 5 0 0 1 6 t o 1 5 5 f f 1 6 a d d r e s s e s 1 5 7 0 0 1 6 t o 1 5 7 f f 1 6 a d d r e s s e s 1 7 9 0 0 1 6 t o 1 7 9 f f 1 6 a d d r e s s e s 1 7 b 0 0 1 6 t o 1 7 b f f 1 6 o s d r o m a d d r e s s o f c h a r a c t e r f o n t d a t a a d 1 6 a d 1 5 a d 1 4 a d 1 3 a d 1 2a d 1 1a d 1 0 a d 9 a d 8 a d 7 a d 6 a d 5 a d 4 a d 3 a d 2a d 1a d 0 o s d r o m a d d r e s s b i t 1l i n e n u m b e r f o n t b i t l i n e n u m b e r / c h a r a c t e r c o d e / f o n t b i t c h a r a c t e r c o d e ( l o w - o r d e r 8 b i t s ) 0 l i n e n u m b e r = 0 a 1 6 t o 1 d 1 6 c h a r a c t e r c o d e = 0 0 0 1 6 t o 1 7 f 1 6 ( 0 7 f 1 6 , 0 8 0 1 6 a n d 1 7 f 1 6 c a n n o t b e u s e d . ) f o n t b i t = 0 : l e f t a r e a 1 : r i g h t a r e a c h a r a c t e r c o d e ( h i g h - o r d e r 1 ) a d d r e s s e s 1 1 4 f e 1 6 t o 1 1 5 0 1 1 6 a d d r e s s e s 1 1 6 f e 1 6 t o 1 1 7 0 1 1 6 a d d r e s s e s 1 3 8 f e 1 6 t o 1 3 9 0 1 1 6 a d d r e s s e s 1 3 a f e 1 6 t o 1 3 b 0 1 1 6 a d d r e s s e s 1 5 4 f e 1 6 a n d 1 5 4 f f 1 6 a d d r e s s e s 1 5 6 f e 1 6 a n d 1 5 6 f f 1 6 a d d r e s s e s 1 7 8 f e 1 6 a n d 1 7 8 f f 1 6 a d d r e s s e s 1 7 a f e 1 6 a n d 1 7 a f f 1 6 97 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.1 gzzCsh54C34b < 89a0 > 740 family mask rom confirmation form single-chip microcomputer m37225m8-xxxsp mitsubishi electric mask rom number receipt date: section head signature supervisor signature ] customer company name tel ( ) date : date issued issuance signature note : please fill in all items marked ] . submitted by supervisor ] 1. confirmation three eproms are required for each pattern if this order is performed by eproms. one floppy disk is required for each pattern if this order is performed by a floppy disk. ordering by eproms if at least two of the three sets of eproms submitted contain identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms. checksum code for entire eprom (hexadecimal notation) eprom type (indicate the type used) (1) set ff 16 in the shaded area. eprom address product nameascii code: 'm37225m8-' 2 7 c 1 0 1 program rom 32k bytes 00000 16 1234567890123456 1234567890123456 1234567890123456 1234567890123456 1234567890123456 1234567890123456 osd rom 1 osd rom 2 1234567890123456 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1234567890123456 0000f 16 08000 16 0ffff 16 11400 16 13bff 16 15400 16 17aff 16 17b00 16 1ffff 16 98 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.1 99 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 (2/3) m = 1 6 4d 1 6 3 = 3 3 1 6 7 = 37 1 6 2 = 3 2 1 6 2 = 32 1 6 5 = 35 1 6 m = 4d 1 6 8 = 38 0 0 0 0 0 1 6 0 0 0 0 1 1 6 0 0 0 0 2 1 6 0 0 0 0 3 1 6 0 0 0 0 4 1 6 0 0 0 0 5 1 6 0 0 0 0 6 1 6 0 0 0 0 7 1 6 a d d r e s s = 1 6 2d 1 6 ff 1 6 ff 1 6 ff 1 6 ff 1 6 ff 1 6 ff 1 6 ff 0 0 0 0 8 1 6 0 0 0 0 9 1 6 0 0 0 0 a 1 6 0 0 0 0 b 1 6 0 0 0 0 c 1 6 0 0 0 0 d 1 6 0 0 0 0 e 1 6 0 0 0 0 f 1 6 a d d r e s s a d d r e s s e s 0 0 0 0 0 1 6 t o 0 0 0 0 f 1 6 s t o r e t h e p r o d u c t n a m e . a s c i i c o d e s m 3 7 2 2 5 m 8 - a r e l i s t e d o n t h e r i g h t . t h e a d d r e s s e s a n d d a t a a r e i n h e x a d e c i m a l n o t a t i o n . a d d r e s s a n d d a t a a r e d e s c r i b e d i n h e x a d e c i m a l n o t a t i o n . i f t h e n a m e o f t h e p r o d u c t c o n t a i n e d i n t h e e p r o m s d o e s n o t m a t c h t h e n a m e o n t h e m a s k r o m c o n f i r m a t i o n f o r m , t h e r o m p r o c e s s i n g i s d i s a b l e d . p l e a s e m a k e s u r e t h e d a t a i s w r i t t e n c o r r e c t l y . g z z s h 5 4 3 4 b < 8 9 a 0 > 7 4 0 f a m i l y m a s k r o m c o n f i r m a t i o n f o r m s i n g l e - c h i p m i c r o c o m p u t e r m 3 7 2 2 5m 8- x x x s p m i t s u b i s h i e l e c t r i c w r i t e t h e a s c i i c o d e s t h a t i n d i c a t e t h e p r o d u c t n a m e o f m 3 7 2 2 5 m 8 t o a d d r e s s e s 0 0 0 0 0 1 6 t o 0 0 0 0 f 1 6 . ( 2 ) n o t e : ] 2 . m a r k s p e c i f i c a t i o n m a r k s p e c i f i c a t i o n m u s t b e s u b m i t t e d u s i n g t h e c o r r e c t f o r m f o r t h e t y p e o f p a c k a g e b e i n g o r d e r e d . f i l l t h e a p p r o p r i a t e m a r k s p e c i f i c a t i o n f o r m ( 4 2 p 4 b f o r m 3 7 2 2 5 m 8 - x x x s p ) a n d a t t a c h t o t h e m a s k r o m c o n f i r m a t i o n f o r m . 3/3 gzzCsh54C34b < 89a0 > 740 family mask rom confirmation form single-chip microcomputer m37225m8-xxxsp mitsubishi electric inputting the character rom e x a m p l e ) t h e f o n t d a t a 6 0 ( s h a d e d a r e a ) o f t h e c h a r a c t e r c o d e 0 a a 1 6 i s s t o r e d i n a d d r e s s 1 0 0 1 0 0 1 0 1 0 1 0 1 0 1 0 0 2 = 1 2 5 5 4 1 6 . 0 a 1 6 0 b 1 6 0 c 1 6 0 d 1 6 0 e 1 6 0 f 1 6 1 0 1 6 1 1 1 6 1 2 1 6 1 3 1 6 1 4 1 6 1 5 1 6 1 6 1 6 1 7 1 6 1 8 1 6 1 9 1 6 1 a 1 6 1 b 1 6 1 c 1 6 1 d 1 6 d b 7d b 6d b 5d b 4 d b 3d b 2d b 1d b 0d b 7d b 6d b 5d b 4d b 3 d b 2d b 1d b 0 l e f t a r e ar i g h t a r e a l i n e n u m b e r c h a r a c t e r c o d e 0 a a 1 6 l i n e n u m b e r n o t e : t h e 1 2 0 - b y t e a d d r e s s e s c o r r e s p o n d i n g t o t h e c h a r a c t e r c o d e s 0 7 f 1 6 , 0 8 0 1 6 a n d 1 f 1 6 i n o s d r o m a r e t h e t e s t d a t a s t o r n i n g a r e a . s e t f f 1 6 t o t h e a r e a ( w e s t o r e s t h e t e s t d a t a t o t h i s a r e a a n d t h e d i f f e r e n t d a t a f r o m f f 1 6 i s s t o r e d f o r t h e a c t u a l p r o d u c t s . ) t h e t e s t d a t a s t o r i n g a r e a : a d d r e s s e s 1 1 0 0 0 1 6 + ( 4 + 2 n ) 5 1 0 0 1 6 + f e 1 6 t o 1 1 0 0 0 1 6 + ( 5 + 2 n ) 5 1 0 0 1 6 + 0 1 1 6 ( n = 0 t o 1 9 ) a d d r e s s e s 1 5 0 0 0 1 6 + ( 4 + 2 n ) 5 1 0 0 1 6 + f e 1 6 a n d 1 5 0 0 0 1 6 + ( 4 + 2 n ) 5 1 0 0 1 6 + f f 1 6 ( n = 0 t o 1 9 ) t h e 5 1 2 0 - b y t e a d d r e s s e s c o r r e s p o n d i n g t o t h e c h a r a c t e r c o d e s 1 8 0 1 6 t o 1 f f 1 6 a r e n o t i n o s d r o m . s e t f f 1 6 t o t h e a r e a , t o o . a d d r e s s e s 1 5 0 0 0 1 6 + ( 5 + 2 n ) 5 1 0 0 1 6 + 0 0 1 6 t o 1 5 0 0 0 1 6 + ( 5 + 2 n ) 5 1 0 0 1 6 + f f 1 6 ( n = 0 t o 1 9 ) o s d r o m a d d r e s s o f c h a r a c t e r f o n t d a t a a d 1 6 a d 1 5 a d 1 4 a d 1 3 a d 1 2a d 1 1a d 1 0 a d 9 a d 8 a d 7 a d 6 a d 5 a d 4 a d 3 a d 2a d 1a d 0 o s d r o m a d d r e s s b i t 1l i n e n u m b e r f o n t b i t l i n e n u m b e r / c h a r a c t e r c o d e / f o n t b i t c h a r a c t e r c o d e ( l o w - o r d e r 8 b i t s ) 0 l i n e n u m b e r = 0 a 1 6 t o 1 d 1 6 c h a r a c t e r c o d e = 0 0 0 1 6 t o 1 7 f 1 6 ( 0 7 f 1 6 , 0 8 0 1 6 a n d 1 7 f 1 6 c a n n o t b e u s e d . ) f o n t b i t = 0 : l e f t a r e a 1 : r i g h t a r e a c h a r a c t e r c o d e ( h i g h - o r d e r 1 ) a d d r e s s e s 1 5 5 0 0 1 6 t o 1 5 5 f f 1 6 a d d r e s s e s 1 5 7 0 0 1 6 t o 1 5 7 f f 1 6 a d d r e s s e s 1 7 9 0 0 1 6 t o 1 7 9 f f 1 6 a d d r e s s e s 1 7 b 0 0 1 6 t o 1 7 b f f 1 6 a d d r e s s e s 1 1 4 f e 1 6 t o 1 1 5 0 1 1 6 a d d r e s s e s 1 1 6 f e 1 6 t o 1 1 7 0 1 1 6 a d d r e s s e s 1 3 8 f e 1 6 t o 1 3 9 0 1 1 6 a d d r e s s e s 1 3 a f e 1 6 t o 1 3 b 0 1 1 6 a d d r e s s e s 1 5 4 f e 1 6 a n d 1 5 4 f f 1 6 a d d r e s s e s 1 5 6 f e 1 6 a n d 1 5 6 f f 1 6 a d d r e s s e s 1 7 8 f e 1 6 a n d 1 7 8 f f 1 6 a d d r e s s e s 1 7 a f e 1 6 a n d 1 7 a f f 1 6 100 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.1 101 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 18. mark specification form 102 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 19. one time prom version m37225ecsp marking m37225ecsp xxxxxxx xxxxxxx is mitsubishi lot number 103 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 20. appendix pin configuration (top view) outline 42p4b p 0 6 / i n t 2 / a - d 4 x o u t h s y n c / p 5 0 v s y n c / p 5 1 p 0 0 / p w m 0 p 0 1 / p w m 1 p 0 2 / p w m 2 p 0 3 / p w m 3 p 0 4 / p w m 4 p 0 5 / p w m 5 p 0 7 / i n t 1 p 2 3 / t i m 3 p 2 4 / t i m 2 p 2 5 p 2 6 p 2 7 d a 1 / p 3 5 p 3 2 / a - d 7 c n v s s x i n v s s 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 r e s e t r / p 5 2 g / p 5 3 b / p 5 4 o u t 1 / p 5 5 p 2 0 / s c l k p 2 1 / s o u t ( /s i n ) p 2 2 / s i n p 1 0 / ou t 2 / a - d 8 p 1 1 / s c l 1 p 1 2 / s c l 2 p 1 3 / s d a 1 p 1 4 / s d a 2 p 1 6 / a - d 2 p 3 0 / a - d 5 p 3 1 / a - d 6 o s c 1 / p 3 3 o s c 2 / p 3 4 v c c p 1 7 / d a 2 /a - d3 p 1 5 / i n t 3 / a - d 1 m 3 7 2 2 5 m 6 - x x x s p m 3 7 2 2 5 m 8 - x x x s p m 3 7 2 2 5 e c s p 104 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 memory map 0 0 0 0 1 6 0 0 c 0 1 6 0 0 f f 1 6 0 1 f f 1 6 s f r a r e a 0 2 1 7 1 6 0 2 1 d 1 6 0 2 4 0 1 6 0 2 e 0 1 6 0 1 0 0 1 6 0 2 4 f 1 6 0 2 c 0 1 6 r o m c o r r e c t i o n f u n c t i o n v e c t o r 1 : a d d r e s s 0 2 c 0 1 6 v e c t o r 2 : a d d r e s s 0 2 e 0 1 6 v e ct o r 3 : a d d r e s s 0 3 0 0 1 6 ? m 3 7 2 5 5 m 6 - x x x s p , m 3 7 2 5 5 m 8 - x x x s p ( 1 0 2 4 b y t e s ) 0 8 7 7 1 6 0 8 0 0 1 6 o s d r a m ( 9 6 b y r e s ) ( s e e n o t e ) 8 0 0 0 1 6 f f f f 1 6 f f d e 1 6 f f 0 0 1 6 i n t e r r u p t v e c t o r a r e a s p e c i a l p a g e a 0 0 0 1 6 m 3 7 2 2 5 m 8 - x x x s p ro m ( 3 2 k b y t e s ) m 3 7 2 2 5 m 6 - x x x s p r o m ( 2 4 k b y t e s ) 0 0 b f 1 6 n o t e : r e f e r t o t a b l e 8 . 1 0 . 3 o s d r a m . 1 0 0 0 0 1 6 1 3 b f f 1 6 1 1 4 0 0 1 6 1 5 4 f f 1 6 1 5 4 0 0 1 6 1 5 6 f f 1 6 1 5 6 0 0 1 6 o s d r o m ( 1 5 k b y t e s ) 1 f f f f 1 6 1 7 8 f f 1 6 1 7 8 0 0 1 6 1 7 a f f 1 6 1 7 a 0 0 1 6 1 5 8 f f 1 6 1 5 8 0 0 1 6 1 5 a f f 1 6 1 5 a 0 0 1 6 1 5 c f f 1 6 1 5 c 0 0 1 6 1 5 e f f 1 6 1 5 e 0 0 1 6 1 6 0 f f 1 6 1 6 0 0 0 1 6 1 6 2 f f 1 6 1 6 2 0 0 1 6 1 6 4 f f 1 6 1 6 4 0 0 1 6 1 6 6 f f 1 6 1 6 6 0 0 1 6 1 6 8 f f 1 6 1 6 8 0 0 1 6 1 6 a f f 1 6 1 6 a 0 0 1 6 1 6 c f f 1 6 1 6 c 0 0 1 6 1 6 e f f 1 6 1 6 e 0 0 1 6 1 7 0 f f 1 6 1 7 0 0 0 1 6 1 7 2 f f 1 6 1 7 2 0 0 1 6 1 7 4 f f 1 6 1 7 4 0 0 1 6 1 7 6 f f 1 6 1 7 6 0 0 1 6 0 4 f f 1 6 0 3 0 0 1 6 z e r o p a g e n o t u s e d 2 p a g e r e g i s t e r ( 1 ) n o t u s e d 2 p a g e r e g i s t e r ( 2 ) n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d 105 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 0 0 0 0 1 6 0 0 c 0 1 6 0 0 f f 1 6 0 1 f f 1 6 s f r a r e a z e r o p a g e 0 2 1 7 1 6 0 2 1 d 1 6 0 2 4 0 1 6 0 1 0 0 1 6 0 2 4 f 1 6 4 0 0 0 1 6 f f f f 1 6 f f d e 1 6 f f 0 0 1 6 r o m ( 4 8 k b y t e ) r a m ( 2 0 4 8 b y t e s ) n o t e : r e f e r t o t a b l e 8 . 1 0 . 1 3 o s d r a m . 1 0 0 0 0 1 6 1 3 b f f 1 6 1 1 4 0 0 1 6 1 5 4 f f 1 6 1 5 4 0 0 1 6 1 5 6 f f 1 6 1 5 6 0 0 1 6 o s d r o m ( 1 5 k b y t e s ) 1 f f f f 1 6 1 7 8 f f 1 6 1 7 8 0 0 1 6 1 7 a f f 1 6 1 7 a 0 0 1 6 1 5 8 f f 1 6 1 5 8 0 0 1 6 1 5 a f f 1 6 1 5 a 0 0 1 6 1 5 c f f 1 6 1 5 c 0 0 1 6 1 5 e f f 1 6 1 5 e 0 0 1 6 1 6 0 f f 1 6 1 6 0 0 0 1 6 1 6 2 f f 1 6 1 6 2 00 1 6 1 6 4 f f 1 6 1 6 4 0 0 1 6 1 6 6 f f 1 6 1 6 6 0 0 1 6 1 6 8 f f 1 6 1 6 8 0 0 1 6 1 6 a f f 1 6 1 6 a 0 0 1 6 1 6 c f f 1 6 1 6 c 0 0 1 6 1 6 e f f 1 6 1 6 e 0 0 1 6 1 7 0 f f 1 6 1 7 0 0 0 1 6 1 7 2 f f 1 6 1 7 2 0 0 1 6 1 7 4 f f 1 6 1 7 4 0 0 1 6 1 7 6 f f 1 6 1 7 6 0 0 1 6 0 0 b f 1 6 ? m 3 7 2 5 5 e c s p 0 2 e 0 1 6 0 2 c 0 1 6 0 7 f f 1 6 0 3 0 0 1 6 0 8 7 7 1 6 0 8 0 0 1 6 0 9 0 0 1 6 0 9 f f 1 6 o s d r a m ( 9 6 b y t e s ) ( s e e n o t e ) n o t u s e d 2 p a g e r e g i s t e r ( 1 ) n o t u s e d 2 p a g e r e g i s t e r ( 2 ) n o t u s e d r o m c o r r e c t i o n f u n c t i o n v e c t o r 1 : a d d r e s s 0 2 c 0 1 6 v e c t o r 2 : a d d r e s s 0 2 e 0 1 6 v e c t o r 3 : a d d r e s s 0 3 0 0 1 6 n o t u s e d n o t u s e d i n t e r r u p t v e c t o r a r e a s p e c i a l p a g e n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d n o t u s e d 106 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 memory map of special function register (sfr) n s f r a r e a ( a d d r e s s e s c 0 1 6 t o d f 1 6 ) d 0 1 6 d 1 1 6 d 2 1 6 d 3 1 6 d 4 1 6 d 5 1 6 d 6 1 6 d 7 1 6 d 8 1 6 d 9 1 6 d a 1 6 d b 1 6 d c 1 6 d d 1 6 d e 1 6 d f 1 6 c 0 1 6 c 1 1 6 c 2 1 6 c 3 1 6 c 4 1 6 c 5 1 6 c 6 1 6 c 7 1 6 c 8 1 6 c 9 1 6 c b 1 6 c c 1 6 c d 1 6 c e 1 6 c f 1 6 c a 1 6 a d d r e s s p o r t p 5 ( p 5 ) o s d p o r t c o n t r o l r e g i s t e r ( p f ) d a 1 - h r e g i s t e r ( d a 1 - h ) d a 1 - l r e g i s t e r ( d a 1 - l ) p w m 0 r e g i s t e r ( p w m 0 ) p o r t p 1 ( p 1 ) p o r t p 1 d i r e c t i o n r e g i s t e r ( d 1 ) p o r t p 3 ( p 3 ) p o r t p 3 d i r e c t i o n r e g i s t e r ( d 3 ) p o r t p 2 ( p 2 ) p o r t p 2 d i r e c t i o n r e g i s t e r ( d 2 ) r e g i s t e r p o r t p 0 ( p 0 ) p o r t p 0 d i r e c t i o n r e g i s t e r ( d 0 ) p w m 1 r e g i s t e r ( p w m 1 ) p w m 2 r e g i s t e r ( p w m 2 ) p w m 3 r e g i s t e r ( p w m 3 ) p w m 4 r e g i s t e r ( p w m 4 ) p w m o u t p u t c o n t r o l r e g i s t e r 1 ( p w ) b 7 b 0 b i t a l l o c a t i o n s t a t e i m m e d i a t e l y a f t e r r e s e t ? 0 0 1 6 b 7 b 0 ? 0 0 1 6 ? 0 0 1 6 0 0 0 ? ? 0 0 0 0? ? ? ??? s e r i a l i / o m o d e r e g i s t e r ( s m ) s e r i a l i / o r e g i s t e r ( s i o ) 0 0 1 6 p o r t p3 5 o u t p u t m o d e c o n t r o l r e g i s t e r ( p 3 s ) t e s t r e g i s t e r i n t e r r u p t i n p u t p o l a r i t y r e g i s t e r ( i p ) p w m o u t p u t c o n t r o l r e g i s t e r 2 ( p n ) i 2 c d a t a s h i f t r e g i s t e r ( s 0 ) i 2 c c o n t r o l r e g i s t e r ( s 1 d ) i 2 c c l o c k c o n t r o l r e g i s t e r ( s 2 ) i 2 c s t a t u s r e g i s t e r ( s 1 ) i 2 c a d d r e s s r e g i s t e r ( s 0 d ) 0 a d c o n v e r s i o n r e g i s t e r ( a d ) a d c o n t r o l r e g i s t e r ( a d c o n ) p 5 2 s e l 00 p 5 3 s e l p 5 4 s e l p 5 5 s e l o u t 2 s e l 0 p 5 2 o u t p 5 3 o u t p 5 4 o u t p 5 5 o u t p 5 0 i n p 5 1 i n 0 0 p 3 5 s p 3 1 sp 3 0 sp 3 5 dp 3 2 dp 3 1 dp 3 0 d p 3 2p 3 1p 3 0 p 3 5 p 3 4 i np 3 3 i n ? ? 0 ? ? 0 0 ?? 0 p w 0 p w 1 p w 2 p w 3 p w 4 p w 5 p w 6 p w 7 p n 2 p n 3 p n 4 ? 0 0 ? ? ? ? ? ? ? ? ? ? 0 0 1 6 0 0 1 6 0 0 1 6 s a d 0 s a d 1 s a d 2 s a d 3 s a d 4 s a d 5 s a d 6 r b w l r b a d 0 a a s a l p i n b b t r x m s t b c 0 b c 1 b c 2 e s o a l s b s e l 0 b s e l 1 1 0 b i t s a d d 1 d 2 d 3 d 4 d 5 d 6 d 7d 0 p n 5 ? 00 00 11 0 0 p o l 3p o l 2p o l 1o c g 1o c g 0 01 1 0 0?? 0 ? 0 0 1 6 0 0 1 6 s m 0 s m 1 s m 2 s m 3 s m 5 s m 6 0 c c r 0 c c r 1 c c r 2 c c r 3 c c r 4 a c k f a s t m o d e a c k b i t a d i n 0 0 0 a d i n 1 a d i n 2 a d s t r a d v r e f ? 0 8 1 6 0 0 1 6 0 0 1 6 ? 0 0 ? 0 0 0 1 0 0 : f i x t o t h i s b i t t o 0 ( d o n o t w r i t e t o 1 ) : b i t a l l o c a t i o n s t a t e i m m e d i a t e l y a f t e r r e s e t f u n c t i o n b i t : n o f u n c t i o n b i t : f i x t o t h i s b i t t o 1 ( d o n o t w r i t e t o 0 ) n a m e : : 0 i m m e d i a t e l y a f t e r r e s e t : i n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t 0 1 ? : 1 i m m e d i a t e l y a f t e r r e s e t 1 0 107 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 f 0 1 6 f 1 1 6 f 2 1 6 f 3 1 6 f 4 1 6 f 5 1 6 f 6 1 6 f 7 1 6 f 8 1 6 f 9 1 6 f a 1 6 f b 1 6 f c 1 6 f d 1 6 f e 1 6 f f 1 6 e 0 1 6 e 1 1 6 e 2 1 6 e 3 1 6 e 4 1 6 e 5 1 6 e 6 1 6 e 7 1 6 e 8 1 6 e 9 1 6 e b 1 6 e c 1 6 e d 1 6 e e 1 6 e f 1 6 e a 1 6 o s d c o n t r o l r e g i s t e r ( o c ) c o l o r r e g i s t e r 5 ( c o 5 ) c o l o r r e g i s t e r 7 ( c o 7 ) c o l o r r e g i s t e r 8 ( c o 8 ) t i m e r 1 ( t 1 ) b l o c k 2 v r e g i s t e r ( b 2 v p ) c o l o r r e g i s t e r 1 ( c o 1 ) c o l o r r e g i s t e r 2 ( c o 2 ) s p r i t e h r e g i s t e r ( s h p ) s p r i t e v r e g i s t e r ( s v p ) b l o c k h r e g i s t e r ( b h p ) b l o c k 1 v r e g i s t e r ( b 1 v p ) t i m e r 2 ( t 2 ) t i m e r 3 ( t 3 ) t i m e r 4 ( t 4 ) t i m e r m o d e r e g i s t e r 1 ( t m 1 ) t i m e r m o d e r e g i s t e r 2 ( t m 2 ) p w m 5 r e g i s t e r ( p w m 5 ) b l o c k 1 c o n t r o l r e g i s t e r ( b 1 c ) i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 ) i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) c o l o r r e g i s t e r 3 ( c o 3 ) c o l o r r e g i s t e r 4 ( c o 4 ) c o l o r r e g i s t e r 6 ( c o 6 ) c p u m o d e r e g i s t e r ( c m ) b 7 b 0 s c 0 s c 1 s c 2 s c 3 o c 0 o c 1 o c 2 t m 2 0 t m 2 1 t m 2 2 t m 2 3 t m 2 4 t m 1 0 t m 1 1 t m 1 2 t m 1 3 t m 1 4 c m 2 t m 1 r t m 2 r t m 3 r t m 4 r o s d r v s c r i t 3 r c k 0 m s r i t 1 r i t 2 r s 1 r t m 1 e t m 2 e t m 3 e t m 4 e o s d e v s c e i t 3 e i t 1 e i t 2 e s 1 e m s e t m 2 5 b 7 b 0 c k 0 ? ? ?? ??? ? 0 f f 1 6 0 7 1 6 f f 1 6 0 7 1 6 ? ? ? 00 ?? ? 00 t m 1 5 0 0 0 01 11 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0?? 3 c 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 s p r i t e c o n t r o l r e g i s t e r ( s c ) o s d i / o p o l a r i t y c o n t r o l r e g i s t e r ( o p c ) t e s t r e g i s t e r t e s t r e g i s t e r a d e a d r s p e s p r i i c r b 2 c 0 b 2 c 1 b 2 c 2 b 2 c 3 b 2 c 4 b 1 c 0 b 1 c 1 b 1 c 2 b 1 c 3 b 1 c 4 0 0 1 6 0 0 1 6 c k 0 00 ?? ? 0?? b l o c k 2 c o n t r o l r e g i s t e r ( b 2 c ) b h p 0 b h p 1 b h p 2 b h p 3 b h p 4 b h p 5 b 1 v p 0 b 1 v p 1 b 1 v p 2 b 1 v p 3 b 1 v p 4 b 1 v p 5 b 1 v p 6 b 1 v p 7 b 2 v p 0 b 2 v p 1 b 2 v p 2 b 2 v p 3 b 2 v p 4 b 2 v p 5 b 2 v p 6 b 2 v p 7 s c 4 s c 5 s c 6 s c 7 s h p 0 s h p 1 s h p 2 s h p 3 s h p 4 s h p 5 s h p 6 s v p 0 s v p 1 s v p 2 s v p 3 s v p 4 s v p 5 s v p 6 s v p 7 o c 3 o c 4 o c 5 o c 6 o c 7 o p c 0 o p c 1 o p c 2 o p c 3 o p c 4 o p c 5 o p c 6 o p c 7 c o 1 1 c o 1 2 c o 1 3 c o 1 5 c o 2 1 c o 2 2 c o 2 3 c o 2 5 c o 1 4 c o 2 4 c o 1 6 c o 2 6 c o 1 0 c o 2 0 c o 3 1 c o 3 2 c o 3 3 c o 3 5c o 3 4 c o 3 6c o 3 0 c o 4 1 c o 4 2 c o 4 3 c o 4 5c o 4 4 c o 4 6c o 4 0 c o 5 1 c o 5 2 c o 5 3 c o 5 5 c o 6 1 c o 6 2 c o 6 3 c o 6 5 c o 5 4 c o 6 4 c o 5 6 c o 6 6 c o 5 0 c o 6 0 c o 7 1 c o 7 2 c o 7 3 c o 7 5c o 7 4 c o 7 6c o 7 0 c o 8 1 c o 8 2 c o 8 3 c o 8 5c o 8 4 c o 8 6c o 8 0 ? ?? ??? ? 0 ? ?? ??? ? 0 ? ?? ??? ? 0 0 0 1 6 ? ?? ??? ? 0 ? ?? ??? ? 0 ? ?? ??? ? 0 ? ?? ??? ? 0 0 0 1 6 0 0 1 6 ? ? n s f r a r e a ( a d d r e s s e s e 0 1 6 t o f f 1 6 ) a d d r e s s r e g i s t e r b i t a l l o c a t i o ns t a t e i m m e d i a t e l y a f t e r r e s e t : f i x t o t h i s b i t t o 0 ( d o n o t w r i t e t o 1 ) : b i t a l l o c a t i o n s t a t e i m m e d i a t e l y a f t e r r e s e t f u n c t i o n b i t : n o f u n c t i o n b i t : f i x t o t h i s b i t t o 1 ( d o n o t w r i t e t o 0 ) n a m e : : 0 i m m e d i a t e l y a f t e r r e s e t : i n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t 0 1 ? : 1 i m m e d i a t e l y a f t e r r e s e t 1 0 i i c e s h p 7 108 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 b 7b 0b 7b 0 2 1 0 1 6 2 1 1 1 6 2 1 2 1 6 2 1 3 1 6 2 1 4 1 6 2 1 5 1 6 2 1 6 1 6 2 1 7 1 6 2 1 8 1 6 2 1 9 1 6 2 1 b 1 6 2 1 c 1 6 2 1 d 1 6 2 1 e 1 6 2 1 f 1 6 2 1 a 1 6 r o m c o r r e c t i o n e n a b l e r e g i s t e r ( r c r ) r o m c o r r e c t i o n a d d r e s s 1 ( h i g h - o r d e r ) r o m c o r r e c t i o n a d d r e s s 1 ( l o w - o r d e r ) ? ? ? ? r o m c o r r e c t i o n a d d r e s s 2 ( h i g h - o r d e r ) r o m c o r r e c t i o n a d d r e s s 2 ( l o w - o r d e r ) r c r 1r c r 0 ? ? ? ? ? 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 0 1 6 2 4 0 1 6 2 4 1 1 6 2 4 2 1 6 2 4 3 1 6 ? ? 2 4 4 1 6 2 4 6 1 6 2 4 5 1 6 l e f t b o r d e r c o n t r o l r e g i s t e r ( l b r ) b b r 0 2 4 7 1 6 2 4 9 1 6 2 4 8 1 6 t e s t r e g i s t e r 0 0 1 6 2 4 a 1 6 ? ? 0 0? ? ? ? 2 4 b 1 6 2 4 c 1 6 ? 2 4 e 1 6 2 4 d 1 6 2 4 f 1 6 ? ? ? r i g h t b o r d e r c o n t r o l r e g i s t e r ( r b r ) t o p b o r d e r c o n t r o l r e g i s t e r ( t b r ) b o t t o m b o r d e r c o n t r o l r e g i s t e r ( b b r ) 0 0 1 6 b b r 1 b b r 2 b b r 3 b b r 4 b b r 5 b b r 6 b b r 7 t b r 0 t b r 1 t b r 2 t b r 3 t b r 4 t b r 5 t b r 6 t b r 7 r b r 0 r b r 1 r b r 2 r b r 3 r b r 4 r b r 5 r b r 6 l b r 0 l b r 1 l b r 2 l b r 3 l b r 4 l b r 5 l b r 6 d a 2 - l r e g i s t e r ( d a 2 l ) d a 2 - h r e g i s t e r ( d a 2 h ) ? ? ? ? ? ? 0 0 1 6 0 0 1 6 n 2 p a g e r e g i s t e r a r e a ( a d d r e s s e s 2 1 0 1 6 t o 2 1 f 1 6 , 2 4 0 1 6 t o 2 4 f 1 6 ) a d d r e s s r e g i s t e r b i t a l l o c a t i o ns t a t e i m m e d i a t e l y a f t e r r e s e t : f i x t o t h i s b i t t o 0 ( d o n o t w r i t e t o 1 ) : b i t a l l o c a t i o ns t a t e i m m e d i a t e l y a f t e r r e s e t f u n c t i o n b i t : n o f u n c t i o n b i t : f i x t o t h i s b i t t o 1 ( d o n o t w r i t e t o 0 ) n a m e : : 0 i m m e d i a t e l y a f t e r r e s e t : i n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t 0 1 ? : 1 i m m e d i a t e l y a f t e r r e s e t 1 0 0 0 0 0 r o m c o r r e c t i o n a d d r e s s 3 (h i g h- o r d e r ) r o m c o r r e c t i o n a d d r e s s 3 (l o w- o r d e r ) 0 0 1 6 0 0 1 6 r c r 2 109 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 internal state of processor status register and program counter at reset b 7 b 0 b 7 b 0 1 r e g i s t e r p r o c e s s o r s t a t u s r e g i s t e r ( p s ) b i t a l l o c a t i o ns t a t e i m m e d i a t e l y a f t e r r e s e t p r o g r a m c o u n t e r ( p c h ) p r o g r a m c o u n t e r ( p c l ) c o n t e n t s o f a d d r e s s f f f f 1 6 c o n t e n t s o f a d d r e s s f f f e 1 6 i z c d b t v n?? ? ? ? ? ? : f i x t o t h i s b i t t o 0 ( d o n o t w r i t e t o 1 ) : b i t a l l o c a t i o n s t a t e i m m e d i a t e l y a f t e r r e s e t f u n c t i o n b i t : n o f u n c t i o n b i t : f i x t o t h i s b i t t o 1 ( d o n o t w r i t e t o 0 ) n a m e : : 0 i m m e d i a t e l y a f t e r r e s e t : i n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t 0 1 ? : 1 i m m e d i a t e l y a f t e r r e s e t 1 0 110 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 structure of register the figure of each register structure describes its functions, contents at reset, and attributes as follows: v a l u e s i m m e d i a t e l y a f t e r r e s e t r e l e a s e b i t a t t r i b u t e s ( n o t e 1 ) ( n o t e 2 ) b i t p o s i t i o n 2 : b i t a t t r i b u t e s t h e a t t r i b u t e s o f c o n t r o l r e g i s t e r b i t s a r e c l a s s i f i e d i n t o 3 t y p e s : r e a d - o n l y , w r i t e - o n l y a n d r e a d a n d w r i t e . i n t h e f i g u r e , t h e s e a t t r i b u t e s a r e r e p r e s e n t e d a s f o l l o w s : : b i t i n w h i c h n o t h i n g i s a s s i g n e d n o t e s 1 : v a l u e s i m m e d i a t e l y a f t e r r e s e t r e l e a s e 0 0 a f t e r r e s e t r e l e a s e 1 1 a f t e r r e s e t r e l e a s e i n d e t e r m i n a t e i n d e t e r m i n a t e a f t e r r e s e t r e l e a s e r e a d e n a b l e d r e a d d i s a b l e d r r r e a d w r i t e e n a b l e d w r i t e d i s a b l e d 0 c a n b e s e t b y s o f t w a r e , b u t 1 c a n n o t b e s e t . w w r i t e w ] b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b a f t e r r e rw c p u m o d e r e g i s t e r 0 , 1 2 3 , 4 0 1 n a m ef u n c t i o n s p r o c e s s o r m o d e b i t s ( c m 0 , c m 1 ) 0 0 : s i n g l e - c h i p m o d e 0 1 : 1 0 : n o t a v a i l a b l e 1 1 : f i x t h e s e b i t s t o 1 . 1 s t a c k p a g e s e l e c t i o n b i t ( s e e n o t e ) ( c m 2 ) 1 b 1 b 0 0 : 0 p a g e 1 : 1 p a g e 1 0 0 5 1 n o t h i n g i s a s s i g n e d . t h i s b i t i s w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 1 . 6 , 7 0 c l o c k s w i t c h b i t s ( c m 6 , c m 7 ) 0 0 : f ( x i n ) = 8 m h z 0 1 : f ( x i n ) = 1 2 m h z 1 0 : f ( x i n ) = 1 6 m h z 1 1 : d o n o t s e t b 7 b 6 c p u m o d e r e g i s t e r ( c p u m ) ( c m ) [ a d d r e s s 0 0 f b 1 6 ] r w rw rw r w rw < e x a m p l e > 111 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 addresses 00c1 16 , 00c3 16 , 00c5 16 address 00c7 16 b7 b6 b5 b4 b3 b2 b1 b0 port pi direction register (di) (i=0,1,2) [addresses 00c1 16, 00c3 16 , 00c5 16 ] b name functions after reset r w port pi direction register 0 0 : port pi 0 input mode 1 : port pi 0 output mode 0 1 0 : port pi 1 input mode 1 : port pi 1 output mode 0 2 0 : port pi 2 input mode 1 : port pi 2 output mode 0 3 0 : port pi 3 input mode 1 : port pi 3 output mode 0 4 0 : port pi 4 input mode 1 : port pi 4 output mode 0 5 0 : port pi 5 input mode 1 : port pi 5 output mode 0 6 0 : port pi 6 input mode 1 : port pi 6 output mode 0 7 0 : port pi 7 input mode 1 : port pi 7 output mode 0 port pi direction register rw rw rw rw rw rw rw rw b 7b 6b 5b 4b 3b 2b 1b 0 p o r t p 3 d i r e c t i o n r e g i s t e r ( d 3 ) [ a d d r e s s 0 0 c 7 1 6 ] bn a m e f u n c t i o n s a f t e r r e s e t r w p o r t p 3 d i r e c t i o n r e g i s t e r 00 : p o r t p 3 0 i n p u t m o d e 1 : p o r t p 3 0 o u t p u t m o d e 0 1 0 : p o r t p 3 1 i n p u t m o d e 1 : p o r t p 3 1 o u t p u t m o d e 0 0 p o r t p 3 d i r e c t i o n r e g i s t e r rw rw rw 2 50 : p o r t p 3 5 i n p u t m o d e 1 : p o r t p 3 5 o u t p u t m o d e p o r t p 3 d i r e c t i o n r e g i s t e r 0rw 7 p o r t p 3 1 o u t p u t m o d e s e l e c t i o n b i t ( p 3 1 s ) 0rw i n d e t e r m i n a t e n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e i n d e t e r m i n a t e . r 3 , 4 0 : p o r t p 3 2 i n p u t m o d e 1 : p o r t p 3 2 o u t p u t m o d e 6 0 : c m o s o u t p u t 1 : n - c h a n n e l o p e n - d r a i n o u t p u t p o r t p 3 0 o u t p u t m o d e s e l e c t i o n b i t ( p 3 0 s ) 0rw 0 : c m o s o u t p u t 1 : n - c h a n n e l o p e n - d r a i n o u t p u t 112 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 address 00c9 16 address 00cb 16 b 7b 6b 5b 4b 3b 2b 1b 0 o s d p o r t c o n t r o l r e g i s t e r ( p f ) [ a d d r e s s 0 0 c b 1 6 ] bn a m ef u n c t i o n s a f t e r r e s e t r w o s d p o r t c o n t r o l r e g i s t e r 0 , 10 r w f i x t h e s e b i t s t o 0 00 2 0 : r s i g n a l o u t p u t 1 : p o r t p 5 2 o u t p u t 0 r w 3p o r t p 5 3 o u t p u t s i g n a l s e l e c t i o n b i t ( p 5 3 s e l ) 0 : g s i g n a l o u t p u t 1 : p o r t p 5 3 o u t p u t 0 r w 4p o r t p 5 4 o u t p u t s i g n a l s e l e c t i o n b i t ( p 5 4 s e l ) 0 : b s i g n a l o u t p u t 1 : p o r t p 5 4 o u t p u t 0 r w 5p o r t p 5 5 o u t p u t s i g n a l s e l e c t i o n b i t ( p 5 5 s e l ) 0 : o u t 1 s i g n a l o u t p u t 1 : p o r t p 5 5 o u t p u t 0 r w 6p o r t p 1 0 o u t p u t s i g n a l s e l e c t i o n b i t ( o u t 2 s e l ) 0 : p o r t p 1 0 s i g n a l o u t p u t 1 : o u t 2 o u t p u t 0 r w p o r t p 5 2 o u t p u t s i g n a l s e l e c t i o n b i t ( p 5 2 s e l ) 70 r w f i x t h i s b i t t o 0 0 b 7b 6b 5b 4b 3b 2b 1b 0 p o r t p 3 5 o u t p u t m o d e c o n t r o l r e g i s t e r ( p 3 s ) [ a d d r e s s 0 0 c 9 1 6 ] bn a m e f u n c t i o n s a f t e r r e s e t r w p o r t p 3 5 o u t p u t m o d e c o n t r o l r e g i s t e r 0 t o 3 i n d e t e r m i n a t e 4 0 : c m o s o u t p u t 1 : n - c h a n n e l o p e n - d r a i n o u t p u t 0 0 f i x t h i s b i t t o 0 r rw r 5 p o r t p 3 5 o u t p u t m o d e s e l e c t i o n b i t ( p 3 5 s ) n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e i n d e t e r m i n a t e . 6 , 7 0rw f i x t h e s e b i t s t o 0 00 0 w 113 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 address 00cd 16 b 7b 6b 5b 4b 3b 2b 1b 0 i n t e r r u p t i n p u t p o l a r i t y r e g i s t e r ( i p ) [ a d d r e s s 0 0 c d 1 6 ] bn a m ef u n c t i o n a f t e r r e s e t r w i n t e r r u p t i n p u t p o l a r i t y r e g i s t e r 0 0 i n t 1 p o l a r i t y s w i t c h b i t ( p o l 1 ) 2 3 4 5 0 : p o s i t i v e p o l a r i t y 1 : n e g a t i v e p o l a r i t y 6 , 7 0r w 0r w 0r w i n t 2 p o l a r i t y s w i t c h b i t ( p o l 2 ) i n t 3 p o l a r i t y s w i t c h b i t ( p o l 3 ) f i x t h e s e b i t s t o 0 . 0w r 0w r 0 , 1 o s d c l o c k s e l e c t i o n b i t s ( o c g 0 , o c g 1 ) 0 r w s i n c e t h e m a i n c l o c k i s u s e d a s t h e c l o c k f o r o s d , t h e o s c i l l a t i o n f r e q u e n c y i s l i m i t e d . b e c a u s e o f t h i s , t h e c h a r a c t e r s i z e i n w i d t h ( h o r i z o n a l ) d i r e c t i o n i s a l s o l i m i t e d . i n t h i s c a s e , p i n s o s c 1 a n d o s c 2 a r e a l s o u s e d a s i n p u t p o r t s p 3 3 a n d p 3 4 r e s p e c t i v e l y . t h e c l o c k f o r o s d i s s u p p l i e d b y c o n n e c t i n g t h e f o l l o w i n g a c r o s s t h e p i n s o s c 1 a n d o s c 2 . h o w e v e r , i t i s n o t c o r r e s p o n d i n g t o t h e b i - s c a n m o d e . a c e r a m i c r e s o n a t o r o n l y f o r o s d a n d a f e e d b a c k r e s i s t o r a q u a r t z - c r y s t a l o s c i l l a t o r o n l y f o r o s d a n d a f e e d b a c k r e s i s t o r b 1 t h e c l o c k f o r o s d i s s u p p l i e d b y c o n n e c t i n g r c o r l c a c r o s s t h e p i n s o s c 1 a n d o s c 2 . h o w e v e r , i t i s n o t c o r r e s p o n d i n g t o t h e b i - s c a n m o d e . f u n c t i o n 00 b 0 o s d o s c i l l a t i o n f r e q u e n c y = f ( x i n ) 0 0 1 1 11 t h e c l o c k f o r o s d i s s u p p l i e d b y c o n n e c t i n g l c a c r o s s t h e p i n s o s c 1 a n d o s c 2 . i n t h e b i - s c a n m o d e , b e s u r e t o s e t t h i s . f i x t h i s b i t t o 0 . 0 : p o s i t i v e p o l a r i t y 1 : n e g a t i v e p o l a r i t y 0 : p o s i t i v e p o l a r i t y 1 : n e g a t i v e p o l a r i t y 0 114 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 address 00d5 16 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 p w m o u t p u t c o n t r o l r e g i s t e r 1 ( p w ) [ a d d r e s s 0 0 d 5 b a f t e r r e s e t rw p w m o u t p u t c o n t r o l r e g i s t e r 1 0 1 2 3 4 0 n a m ef u n c t i o n s d a 1 , d a 2 , p w m c o u n t s o u r c e s e l e c t i o n b i t ( p w 0 ) 0 : c o u n t s o u r c e s u p p l y 1 : c o u n t s o u r c e s t o p p 0 0 / p w m 0 o u t p u t s e l e c t i o n b i t ( p w 2 ) 0 : p 0 0 o u t p u t 1 : p w m 0 o u t p u t p 0 1 / p w m 1 o u t p u t s e l e c t i o n b i t ( p w 3 ) 0 : p 0 1 o u t p u t 1 : p w m 1 o u t p u t p 0 2 / p w m 2 o u t p u t s e l e c t i o n b i t ( p w 4 ) 0 : p 0 2 o u t p u t 1 : p w m 2 o u t p u t 5 p 0 3 / p w m 3 o u t p u t s e l e c t i o n b i t ( p w 5 ) 0 : p 0 3 o u t p u t 1 : p w m 3 o u t p u t 6 p 0 4 / p w m 4 o u t p u t s e l e c t i o n b i t ( p w 6 ) 0 : p 0 4 o u t p u t 1 : p w m 4 o u t p u t d a 1 o u t p u t / p 3 5 s e l e c t i o n b i t ( p w 1 ) 0 : d a 1 o u t p u t 1 : p 3 5 o u t p u t 7 p 0 5 / p w m 5 o u t p u t s e l e c t i o n b i t ( p w 7 ) 0 : p 0 5 o u t p u t 1 : p w m 5 o u t p u t 0 0 0 0 0 0 0 1 6 ] rw rw rw rw rw rw rw rw b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 p w m o u t p u t c o n t r o l r e g i s t e r 2 ( p n ) [ a d d r e s s 0 0 d 6 b a f t e r r e s e t rw p w m o u t p u t c o n t r o l r e g i s t e r 2 0 , 1 2 3 4 0 n a m ef u n c t i o n s d a 1 o u t p u t p o l a r i t y s e l e c t i o n b i t ( p n 3 ) 0 : p o s i t i v e p o l a r i t y 1 : n e g a t i v e p o l a r i t y p w m o u t p u t p o l a r i t y s e l e c t i o n b i t ( p n 4 ) f i x t h e s e b i t s t o 0 . d a 2 o u t p u t p o l a r i t y s e l e c t i o n b i t ( p n 5 ) 0 : o u t p u t l o w 1 : o u t p u t h i g h 6 , 7 0 0 0 0 f i x t h e s e b i t s t o 0 . 0 : p o s i t i v e p o l a r i t y 1 : n e g a t i v e p o l a r i t y 1 6 ] r rw rw rw rw 0 0 0 0 5 p 1 7 / d a 2 o u t p u t s e l e c t i o n b i t ( p n 5 ) 0 : p 1 7 1 : d a 2 0 rw w address 00d6 16 115 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 address 00d7 16 b 7b 6b 5b 4b 3b 2b 1b 0 i 2 c d a t a s h i f t r e g i s t e r ( s 0 ) [ a d d r e s s 0 0 d 7 1 6 ] b f u n c t i o n sa f t e r r e s e trw i c d a t a s h i f t r e g i s t e r 0 t o 7 t h i s i s a n 8 - b i t s h i f t r e g i s t e r t o s t o r e r e c e i v e d a t a a n d w r i t e t r a n s m i t d a t a . i n d e t e r m i n a t e 2 n o t e : 2 t o w r i t e d a t a i n t o t h e i c d a t a s h i f t r e g i s t e r a f t e r s e t t i n g t h e m s t b i t t o 0 ( s l a v e m o d e ) , k e e p a n i n t e r v a l o f 8 m a c h i n e c y c l e s o r m o r e . n a m e d 0 t o d 7 rw address 00d8 16 b 7b 6b 5b 4b 3b 2b 1b 0 0 r e a d / w r i t e b i t ( r b w ) 1 t o 7 s l a v e a d d r e s s ( s a d 0 t o s a d 6 ) < o n l y i n 1 0 - b i t a d d r e s s i n g ( i n s l a v e ) m o d e > t h e l a s t s i g n i f i c a n t b i t o f a d d r e s s d a t a i s c o m p a r e d . 0 : w a i t t h e f i r s t b y t e o f s l a v e a d d r e s s a f t e r s t a r t c o n d i t i o n ( r e a d s t a t e ) 1 : w a i t t h e f i r s t b y t e o f s l a v e a d d r e s s a f t e r r e s t a r t c o n d i t i o n ( w r i t e s t a t e ) 0 0 < i n b o t h m o d e s > t h e a d d r e s s d a t a i s c o m p a r e d . i 2 c a d d r e s s r e g i s t e r i 2 c a d d r e s s r e g i s t e r ( s 0 d ) [ a d d r e s s 0 0 d 8 1 6 ] b n a m e f u n c t i o n s a f t e r r e s e t r w r r w 116 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 address 00d9 16 address 00da 16 b 7b 6b 5b 4b 3b 2b 1b 0 i 2 c s t a t u s r e g i s t e r ( s 1 ) [ a d d r e s s 0 0 d 9 1 6 ] i 2 c s t a t u s r e g i s t e r 0 3 4 5 6 , 7 b 7 b 6 0 0 : s l a v e r e c i e v e m o d e 0 1 : s l a v e t r a n s m i t m o d e 1 0 : m a s t e r r e c i e v e m o d e 1 1 : m a s t e r t r a n s m i t m o d e 1 2 0 0 0 1 0 b n a m e f u n c t i o n s a f t e r r e s e t r w c o m m u n i c a t i o n m o d e s p e c i f i c a t i o n b i t s ( t r x , m s t ) 0 : b u s f r e e 1 : b u s b u s y b u s b u s y f l a g ( b b ) 0 : i n t e r r u p t r e q u e s t i s s u e d 1 : n o i n t e r r u p t r e q u e s t i s s u e d i 2 c - b u s i n t e r f a c e i n t e r r u p t r e q u e s t b i t ( p i n ) 0 : n o t d e t e c t e d 1 : d e t e c t e d a r b i t r a t i o n l o s t d e t e c t i n g f l a g ( a l ) ( s e e n o t e ) 0 : a d d r e s s m i s m a t c h 1 : a d d r e s s m a t c h s l a v e a d d r e s s c o m p a r i s o n f l a g ( a a s ) ( s e e n o t e ) 0 : n o g e n e r a l c a l l d e t e c t e d 1 : g e n e r a l c a l l d e t e c t e d g e n e r a l c a l l d e t e c t i n g f l a g ( a d 0 ) ( s e e n o t e ) 0 : l a s t b i t = 0 1 : l a s t b i t = 1 l a s t r e c e i v e b i t ( l r b ) ( s e e n o t e ) n o t e : t h e s e b i t s a n d f l a g s c a n b e r e a d o u t , b u t c a n n n o t b e w r i t t e n . i n d e t e r m i n a t e r r r r rw r w 0 r w ( s e e n o t e ) ( s e e n o t e ) ( s e e n o t e ) ( s e e n o t e ) b 7b 6b 5b 4b 3b 2b 1b 0 0 t o 2 b i t c o u n t e r ( n u m b e r o f t r a n s m i t / r e c i e v e b i t s ) ( b c 0 t o b c 2 ) b 2 b 1 b 0 0 0 0 : 8 0 0 1 : 7 0 1 0 : 6 0 1 1 : 5 1 0 0 : 4 1 0 1 : 3 1 1 0 : 2 1 1 1 : 1 3 i 2 c - b u s i n t e r f a c e u s e e n a b l e b i t ( e s o ) 0 : d i s a b l e d 1 : e n a b l e d 4d a t a f o r m a t s e l e c t i o n b i t ( a l s ) 0 : a d d r e s s i n g f o r m a t 1 : f r e e d a t a f o r m a t 5a d d r e s s i n g f o r m a t s e l e c t i o n b i t ( 1 0 b i t s a d ) 0 : 7 - b i t a d d r e s s i n g f o r m a t 1 : 1 0 - b i t a d d r e s s i n g f o r m a t 6 , 7 c o n n e c t i o n c o n t r o l b i t s b e t w e e n i c - b u s i n t e r f a c e a n d p o r t s ( b s e l 0 , b s e l 1 ) b 7 b 6 c o n n e c t i o n p o r t ( s e e n o t e ) 0 0 : n o n e 0 1 : s c l 1 , s d a 1 1 0 : s c l 2 , s d a 2 1 1 : s c l 1 , s d a 1 , s c l 2 , s d a 2 0 0 0 0 0 i 2 c c o n t r o l r e g i s t e r ( s 1 d ) [ a d d r e s s 0 0 d a 1 6 ] i 2 c c o n t r o l r e g i s t e r b n a m e f u n c t i o n s a f t e r r e s e t r w 2 r w r w r w r w r w n o t e : w h e n u s i n g p o r t s p 1 1 - p 1 4 a s i 2 c - b u s i n t e r f a c e , t h e o u t p u t s t r u c t u r e c h a n g e s a u t o m a t i c a l l y f r o m c m o s o u t p u t t o n - c h a n n e l o p e n - d r a i n o u t p u t . 117 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 address 00db 16 b 7b 6b 5b 4b 3b 2b 1b 0 i 2 c c l o c k c o n t r o l r e g i s t e r ( s 2 ) [ a d d r e s s 0 0 d b 1 6 ] i 2 c c l o c k c o n t r o l r e g i s t e r 0 t o 4 s c l f r e q u e n c y c o n t r o l b i t s ( c c r 0 t o c c r 4 ) 7 5 6 s c l m o d e s p e c i f i c a t i o n b i t ( f a s t m o d e ) 0 : s t a n d a r d c l o c k m o d e 1 : h i g h - s p e e d c l o c k m o d e 0 s t a n d a r d c l o c k m o d e b n a m e f u n c t i o n s a f t e r r e s e t r w 0 0 0 a c k b i t ( a c k b i t ) a c k c l o c k b i t ( a c k ) 0 : a c k i s r e t u r n e d . 1 : a c k i s n o t r e t u r n e d . 0 : n o a c k c l o c k 1 : a c k c l o c k h i g h s p e e d c l o c k m o d e s e t u p d i s a b l e d s e t u p d i s a b l e d 0 0 t o 0 2 s e t u p d i s a b l e d 3 3 3 0 3 s e t u p d i s a b l e d 2 5 0 0 4 1 0 0 4 0 0 ( s e e n o t e ) 0 5 8 3 . 31 6 6 0 6 5 0 0 / c c r v a l u e 1 0 0 0 / c c r v a l u e . . . 1 7 . 2 3 4 . 5 1 d 1 6 . 63 3 . 3 1 e 1 6 . 1 3 2 . 3 1 f ( a t f = 4 m h z , u n i t : k h z ) n o t e : a t 4 0 0 k h z i n t h e h i g h - s p e e d c l o c k m o d e , t h e d u t y i s a s b e l o w . 0 p e r i o d : 1 p e r i o d = 3 : 2 i n t h e o t h e r c a s e s , t h e d u t y i s a s b e l o w . 0 p e r i o d : 1 p e r i o d = 1 : 1 s e t u p v a l u e o f c c r 4 C c c r 0 r w r w r w r w 118 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 address 00dc 16 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 s e r i a l i / o m o d e r e g i s t e r ( s m ) [ a d d r e s s 0 0 d c 1 6 ] bn a m ef u n c t i o n s a f t e r r e s e t rw s e r i a l i / o m o d e r e g i s t e r 0 , 1i n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s ( s m 0 , s m 1 ) b 1 b 0 0 0 : f ( x i n ) / 4 0 1 : f ( x i n ) / 1 6 1 0 : f ( x i n ) / 3 2 1 1 : f ( x i n ) / 6 4 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t ( s m 2 ) 3 s e r i a l i / o p o r t s e l e c t i o n b i t ( s m 3 ) 6 5 t r a n s f e r d i r e c t i o n s e l e c t i o n b i t ( s m 5 ) 0 : p 2 0 , p 2 1 1 : s c l k , s o u t 0 : e x t e r n a l c l o c k 1 : i n t e r n a l c l o c k 0 : l s b f i r s t 1 : m s b f i r s t 0 0 0 0 0 0 rw rw rw r w rw rw 4 f i x t h i s b i t t o 0 . 7 n o t h i n g i s a s s i g n e d . t h i s b i t i s a w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . 0r s e r i a l i n p u t p i n s e l e c t i o n b i t ( s m 6 ) 0 : i n p u t s i g n a l f r o m s i n p i n . 1 : i n p u t s i g n a l f r o m s o u t p i n . 0 a - d c o n t r o l r e g i s t e r b 7b 6b 5b 4b 3b 2b 1b 0 a - d c o n t r o l r e g i s t e r ( a d c o n ) [ a d d r e s s 0 0 d f 1 6 ] b a f t e r r e s e t rw 0 t o 2 a n a l o g i n p u t p i n s e l e c t i o n b i t s ( a d i n 0 t o a d i n 2 ) n a m ef u n c t i o n s b 2 b 1 b 0 0 0 0 : a - d 1 0 0 1 : a - d 2 0 1 0 : a - d 3 0 1 1 : a - d 4 1 0 0 : a - d 5 1 0 1 : a - d 6 1 1 0 : a - d 7 1 1 1 : a - d 8 4 v c c c o n n e c t i o n s e l e c t i o n b i t ( a d v r e f ) 0 : o f f 1 : o n 0 0 6 n o t h i n g i s a s s i g n e d . t h i s b i t i s a w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s i n d e t e r m i n a t e . rw rw r 3 a - d c o n v e r s i o n c o m p l e t i o n b i t ( a d s t r ) 0 : c o n v e r s i o n i n p r o g r e s s 1 : c o n v e r t i o n c o m p l e t e d 1 rw 7 f i x t h i s b i t t o 0 . rw 00 i n d e t e r m i n a t e 5 f i x t h i s b i t t o 0 . rw 0 0 address 00df 16 119 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 address 00e0 16 b 7b 6b 5b 4b 3b 2b 1b 0 b l o c k i v r e g i s t e r ( b i v p ) ( i = 1 , 2 ) [ a d d r e s s e s 0 0 e 1 1 6 a n d 0 0 e 2 1 6 ] bn a m ef u n c t i o n sa f t e r r e s e tr w b l o c k i v r e g i s t e r 0 t o 7 c o n t r o l b i t s o f v e r t i c a l d i s p l a y s t a r t p o s i t i o n s ( b i v p 0 t o b i v p 7 ) ( s e e n o t e 1 ) i n d e t e r m i n a t e rw n o t e : s e t v a l u e s e x c e p t 0 0 1 6 t o b i v p . v e r t i c a l d i s p l a y s t a r t p o s i t i o n s = h d e f + h 5 n ( n : s e t t i n g v a l u e , h d e f : 1 7 h , h : h s y n c ) addresses 00e1 16 and 00e2 16 b 7b 6b 5b 4b 3b 2b 1b 0 h o r i z o n t a l p o s i t i o n r e g i s t e r ( h p ) [ a d d r e s s 0 0 e 0 1 6 ] bn a m ef u n c t i o n s b l o c k h r e g i s t e r c o n t r o l b i t s o f h o r i z o n t a l d i s p l a y s t a r t p o s i t i o n s ( b h p 0 t o b h p 5 ) ( s e e n o t e 1 ) 0 t o 5 n o t e : t h e s e t t i n g v a l u e s y n c h r o n i z e s w i t h t h e v s y n c . 6 , 7 n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . a f t e r r e s e t rw 0rw 0r h o r i z o n t a l d i s p l a y s t a r t p o s i t i o n s = t d e f 1 + 4 t o s c 5 n ( n : s e t t i n g v a l u e , t d e f 1 : 3 1 t o s c , t o s c : o s d o s c i l l a t i o n c y c l e ) 120 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 address 00e3 16 b 7b 6b 5b 4b 3b 2b 1b 0 s p r i t e c o n t r o l r e g i s t e r ( s c ) [ a d d r e s s 0 0 e 3 1 6 ] bn a m ef u n c t i o n s a f t e r r e s e t r w s p r i t e c o n t r o l r e g i s t e r 0 , 1 4 , 5 s p r i t e f o n t 1 c o l o r r e g i s t e r s p e c i f i c a t i o n b i t ( s c 0 , s c 1 ) 0 0 w r w r n o t e : t h i s b i t i s v a l i d w h e n b i t 0 o f t h e o s d c o n t r o l r e g i s t e r t o 1 . 2 , 3 s p r i t e f o n t 2 c o l o r r e g i s t e r s p e c i f i c a t i o n b i t ( s c 2 , s c 3 ) 0w r 6 , 7 s p r i t e / r a s t e r p a t t e r n i n g c o n t r o l b i t ( s c 6 , s c 7 ) ( s e e n o t e ) 0w r s p r i t e f o n t s e l e c t i o n b i t ( s c 4 , s c 5 ) s c 5 s c 4 c h a r a c t e r c o d e s p r i t e 1s p r i t e 2 0 0 1 1 0 1 0 1 f 8 1 6 f a 1 6 f c 1 6 f e 1 6 f 9 1 6 f b 1 6 f d 1 6 f f 1 6 s c 1 @ s c 0 00 : c o l o r r e g i s t e r 1 01 : c o l o r r e g i s t e r 2 10 : c o l o r r e g i s t e r 3 11 : c o l o r r e g i s t e r 4 s c 3 @ s c 2 00 : c o l o r r e g i s t e r 1 01 : c o l o r r e g i s t e r 2 10 : c o l o r r e g i s t e r 3 11 : c o l o r r e g i s t e r 4 s c 7 @ s c 6 00 : d i s p l a y o f f 01 : d o n o t s e t 10 : s p r i t e d i s p l a y 11 : r a s t e r p a t t e r n i n g d i s p l a y 121 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 address 00e4 16 b 7b 6b 5b 4b 3b 2b 1b 0 s p r i t e h r e g i s t e r ( s h p ) [ a d d r e s s 0 0 e 4 1 6 ] bn a m ef u n c t i o n s s p r i t e h r e g i s t e r 0 t o 7 h o r i z o n t a l d i s p l a y s t a r t p o s i t i o n c o n t r o l b i t s o f s p r i t e o s d ( s h p 0 t o s h p 7 ) h o r i z o n t a l d i s p l a y s t a r t p o s i t i o n = t d e f 2 + 2 t o s c n ( n : s e t t i n g v a l u e , t d e f 2 : 2 t o s c , t o s c : o s d o s c i l l a t i o n c y c l e ) a f t e r r e s e trw rw 0 n o t e s 1 : s e t v a l u e s e x c e p t 0 0 1 6 t o 0 2 1 6 t o s h p . 2 : w h e n s e l e c t i n g r a s t e r p a t t e r n i n g d i s p l a y , s e t t i n g v a l u e i s s y n c h r o n i z e d w i t h v s y n c s i g n a l ; w h e n s e l e c t i n g s p r i t e d i s p l a y , i t i s n o t s y n c h r o n i z e d . 5 address 00e5 16 b 7b 6b 5b 4b 3b 2b 1b 0 s p r i t e v r e g i s t e r ( s v p ) [ a d d r e s s 0 0 e 5 1 6 ] bn a m ef u n c t i o n s s p r i t e v r e g i s t e r 0 t o 7 h o r i z o n t a l d i s p l a y s t a r t p o s i t i o n c o n t r o l b i t s o f s p r i t e o s d ( s v p 0 t o s v p 7 ) ( s e e n o t e 1 ) h o r i z o n t a l d i s p l a y s t a r t p o s i t i o n = h d e f + h 5 n ( n : s e t t i n g v a l u e , h d e f : 1 7 h , h : h s y n c ) n o t e : s e t v a l u e s e x c e p t 0 0 1 6 t o t h e s v p . a f t e r r e s e trw rw i n d e t e r m i n a t e 122 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 addresses 00e6 16 to 00e9 16 and 00ec 16 to 00ef 16 b 7b 6b 5b 4b 3b 2b 1b 0 c o l o r r e g i s t e r i ( c o 1 t o c o 8 ) ( i = 1 t o 8 ) [ a d d r e s s e s 0 0 e 6 1 6 t o 0 0 e 9 1 6 , 0 0 e c 1 6 t o 0 0 e f 1 6 ] bn a m ef u n c t i o n s a f t e r r e s e t r w c o l o r r e g i s t e r i 0 i n d e t e r m i n a t e r w 1 g s i g n a l o u t p u t s e l e c t i o n b i t ( c o i 1 ) 0 : n o o u t p u t 1 : o u t p u t r w 2 b s i g n a l o u t p u t s e l e c t i o n b i t ( c o i 2 ) 0 : n o o u t p u t 1 : o u t p u t r w 3r s i g n a l o u t p u t ( b a c k g r o u n d ) s e l e c t i o n b i t ( c o i 3 ) 0 : n o o u t p u t 1 : o u t p u t r w 4 g s i g n a l o u t p u t ( b a c k g r o u n d ) s e l e c t i o n b i t ( c o i 4 ) 0 : n o o u t p u t 1 : o u t p u t r w 5b s i g n a l o u t p u t ( b a c k g r o u n d ) s e l e c t i o n b i t ( c o i 5 ) 0 : n o o u t p u t 1 : o u t p u t r w 6 o u t 1 o u t p u t c o n t r o l b i t ( c o i 6 ) 0 : c h a r a c t e r o u t p u t 1 : b l a n k o u t p u t r w 7 0 r @ r s i g n a l o u t p u t s e l e c t i o n b i t ( c o i 0 ) 0 : n o o u t p u t 1 : o u t p u t n o t h i n g i s a s s i n e d . t h i s b i t i s a w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . i n d e t e r m i n a t e i n d e t e r m i n a t e i n d e t e r m i n a t e i n d e t e r m i n a t e i n d e t e r m i n a t e i n d e t e r m i n a t e 123 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 address 00ea 16 b 3b 2( s e e n o t e s 3 a n d 4 ) 00 : s t a n d a r d 01 : s t a n d a r d + 1 t o s c 10 : s t a n d a r d + 2 t o s c 11 : s t a n d a r d + 3 t o s c b 7b 6b 5b 4b 3b 2b 1b 0 o s d c o n t r o l r e g i s t e r ( o c ) [ a d d r e s s 0 0 e a 1 6 ] bn a m e f u n c t i o n s a f t e r r e s e t r w o s d c o n t r o l r e g i s t e r 0 o s d c o n t r o l b i t ( o c 0 ) ( s e e n o t e 1 ) 0 : a l l - b l o c k s d i s p l a y o f f 1 : a l l - b l o c k s d i s p l a y o n 0 1 b o r d e r t y p e s e l e c t i o n b i t ( o c 1 ) 0 : a l l b o r d e r e d 1 : s h a d o w b o r d e r e d ( s e e n o t e 2 ) 0 2 , 3 0 4w i n d o w c o n t r o l b i t ( o c 4 ) 0 w i n d o w h o r i z o n t a l p o s i t i o n m i n u t e a d j u s t m e n t b i t ( o c 2 , o c 3 ) rw rw rw rw 6r a s t e r c o l o r o u t 1 c o n t r o l b i t ( o c 6 ) 0 : w i n d o w o f f 1 : w i n d o w o n 0rw 5 s c a n m o d e s e l e c t i o n b i t ( o c 5 ) 0rw 0 : n o r m a l s c a n m o d e 1 : b i - s c a n m o d e ( s e e n o t e 5 ) n o t e s 1 : e v e n t h i s b i t i s s w i t c h e d d u r i n g d i s p l a y , t h e d i s p l a y s c r e e n r e m a i n s u n c h a n g e d u n t i l a r i s i n g ( f a l l i n g ) o f t h e n e x t v s y n c . 2 : s h a d o w b o r d e r i s o u t p u t a t r i g h t a n d b o t t o m s i d e o f t h e f o n t . 3 : t o s c = o s d o s c i l l a t i o n c y c l e 4 : t h e s e b i t s a r e v a l l i d f o r b o t h l e f t b o r d e r a n d r i g h t b o r d e r ( f o r d e t a i l , r e f e r t o ( 8 ) w i n d o w f u n c t i o n . ) 5 : w h e n s e t t i n g t o b i - s c a n m o d e , c o n n e c t l c b e t w e e n p i n s o s c 1 a n d o s c 2 . 0 : n o o u t p u t 1 : o u t p u t 7r a s t e r c o l o r o u t 2 c o n t r o l b i t ( o c 7 ) 0rw 0 : n o o u t p u t 1 : o u t p u t 124 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 address 00eb 16 b 7b 6b 5b 4b 3b 2b 1b 0 o s d i / o p o l a r i t y r e g i s t e r ( o p c ) [ a d d r e s s 0 0 e b 1 6 ] b n a m ef u n c t i o n s a f t e r r e r w o s d i / o p o l a r i t y r e g i s t e r 0h s y n c i n p u t p o l a r i t y s w i t c h b i t ( o p c 0 ) 0 : p o s i t i v e p o l a r i t y i n p u t 1 : n e g a t i v e p o l a r i t y i n p u t 0 1 0 : p o s i t i v e p o l a r i t y i n p u t 1 : n e g a t i v e p o l a r i t y i n p u t 0 2r / g / b o u t p u t p o l a r i t y s w i t c h b i t ( o p c 2 ) 0 : p o s i t i v e p o l a r i t y o u t p u t 1 : n e g a t i v e p o l a r i t y o u t p u t 0 3 0 v s y n c i n p u t p o l a r i t y s w i t c h b i t ( o p c 1 ) r w r w r w r w 4 o u t 2 o u t p u t p o l a r i t y s w i t c h b i t ( o p c 4 ) 0 : p o s i t i v e p o l a r i t y o u t p u t 1 : n e g a t i v e p o l a r i t y o u t p u t 0 5r a s t e r c o l o r r c o n t r o l b i t ( o p c 5 ) 0 : n o o u t p u t 1 : o u t p u t 0 6r a s t e r c o l o r g c o n t r o l b i t ( o p c 6 ) 0 7r a s t e r c o l o r b c o n t r o l b i t ( o p c 7 ) 0 : n o o u t p u t 1 : o u t p u t 0 r w r w r w r w o u t 1 o u t p u t p o l a r i t y s w i t c h b i t ( o p c 3 ) 0 : p o s i t i v e p o l a r i t y o u t p u t 1 : n e g a t i v e p o l a r i t y o u t p u t 0 : n o o u t p u t 1 : o u t p u t 125 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 address 00f4 16 address 00f5 16 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 t i m e r m o d e r e g i s t e r 1 ( t m 1 ) [ a d d r e s s 0 0 f 4 1 6 ] b a f t e r r e s e t w t i m e r m o d e r e g i s t e r 1 0 1 2 3 4 n a m e f u n c t i o n s t i m e r 1 c o u n t s o u r c e s e l e c t i o n b i t 1 ( t m 1 0 ) 0 : f ( x i n ) / 1 6 1 : f ( x i n ) / 4 0 9 6 t i m e r 2 c o u n t s o u r c e s e l e c t i o n b i t 1 ( t m 1 1 ) 0 : i n t e r r u p t c l o c k s o u r c e 1 : e x t e r n a l c l o c k f r o m t i m 2 p i n t i m e r 1 c o u n t s t o p b i t ( t m 1 2 ) 0 : c o u n t s t a r t 1 : c o u n t s t o p t i m e r 2 c o u n t s t o p b i t ( t m 1 3 ) 0 : c o u n t s t a r t 1 : c o u n t s t o p t i m e r 2 i n t e r n a l c o u n t s o u r c e s e l e c t i o n b i t 2 ( t m 1 4 ) r 0 0 0 0 0 w r w r w r w r w r 0 : f ( x i n ) / 1 6 1 : t i m e r 1 o v e r f l o w 5 < a t e x e c u t i o n o f s t p i n s t r u c t i o n > t i m e r s 3 a n d 4 a u t o s e t d i s a b l e b i t ( t m 1 5 ) 0 : a u t o s e t e n a b l e d 1 : a u t o s e t d i s a b l e d 0 w r 6 , 7n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . 0 r b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 t i m e r m o d e r e g i s t e r 2 ( t m 2 ) [ a d d r e s s 0 0 f 5 1 6 ] b a f t e r r e s e t rw t i m e r m o d e r e g i s t e r 2 0 n a m e f u n c t i o n s t i m e r 3 c o u n t s o u r c e s e l e c t i o n b i t ( t m 2 0 ) 0 rw 1 t i m e r 4 i n t e r n a l i n t e r r u p t c o u n t s o u r c e s e l e c t i o n b i t ( t m 2 1 ) 0 rw 2 3 t i m e r 3 c o u n t s t o p b i t ( t m 2 2 ) 0 : c o u n t s t a r t 1 : c o u n t s t o p t i m e r 4 c o u n t s t o p b i t ( t m 2 3 ) 0 : c o u n t s t a r t 1 : c o u n t s t o p 0 0 4 t i m e r 4 c o u n t s o u r c e s e l e c t i o n b i t ( t m 2 4 ) 0 : i n t e r n a l c l o c k s o u r c e 1 : f ( x i n ) / 2 0 5 t i m e r 3 e x t e r n a l c o u n t s o u r c e s e l e c t i o n b i t ( t m 2 5 ) 0 : t i m 3 p i n i n p u t 1 : h s y n c p i n i n p u t 0 rw rw rw rw 0 : f ( x i n ) / 1 6 1 : e x t e r n a l c l o c k s o u r c e 0 : t i m e r 3 o v e r f l o w s i g n a l 1 : f ( x i n ) / 1 6 6 , 7n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . 0 r 126 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 addresses 00f9 16 and 00fa 16 address 00fb 16 b 2b 1b 0d i s p l a y m o d e 5 00d i s p l a y o f f 00 1 o s d m o d e ( n o b o r d e r ) 01 0 b u t t o n m o d e ( n o b o r d e r ) 10 1 o s d m o d e ( b o r d e r ) 11 0 b u t t o n m o d e ( b o r d e r ) b 7b 6b 5b 4b 3b 2b 1b 0 b l o c k i c o n t r o l r e g i s t e r ( b i c ) ( i = 1 , 2 ) [ a d d r e s s e s 0 0 f 9 1 6 , 0 0 f a 1 6 ] bn a m e f u n c t i o n s a f t e r r e s e t r w b l o c k i c o n t r o l r e g i s t e r 0 t o 2 d i s p l a y m o d e s e l e c t i o n b i t s ( b i c 0 t o b i c 2 ) i n d e t e r m i n a t e 3, 4 d o t s i z e s e l e c t i o n b i t ( b i c 3 , b i c 4 ) rw rw n o t e s 1 : t o s c = o s d o s c i l l a t i o n c y c l e 2 : h = h s y nc b 4b 3d o t s i z e 00 1 t o s c 5 1 h 01 d o n o t s e t 10 2 t o s c 5 2 h 11 3 t o s c 5 3 h 5 t o 7 0 n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . r i n d e t e r m i n a t e c p u m o d e r e g i s t e r b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 b a f t e r r e s e t r w 0 , 1 2 3 t o 5 0 1 n a m e f u n c t i o n s p r o c e s s o r m o d e b i t s ( c m 0 , c m 1 ) 0 0 : s i n g l e - c h i p m o d e 0 1 : 1 0 : n o t a v a i l a b l e 1 1 : f i x t h e s e b i t s t o 1 . 1 s t a c k p a g e s e l e c t i o n b i t ( c m 2 ) ( s e e n o t e ) 1 b 1 b 0 0 : 0 p a g e 1 : 1 p a g e 1 0 0 6 , 7 0 c p u m o d e r e g i s t e r ( c m ) [ a d d r e s s 0 0 f b 1 6 ] r w r w r w r w n o t e : t h i s b i t i s s e t t o 1 a f t e r t h e r e s e t r e l e a s e . 1 0 0 f i x t h e s e b i t s t o 0 . 127 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 address 00fc 16 address 00fd 16 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) [ a d d r e s s 0 0 f c bn a m e f u n c t i o n s a f t e r r e s e t rw i n t e r r u p t r e q u e s t r e g i s t e r 1 0 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d t i m e r 1 i n t e r r u p t r e q u e s t b i t ( t m 1 r ) 1 t i m e r 2 i n t e r r u p t r e q u e s t b i t ( t m 2 r ) 2 t i m e r 3 i n t e r r u p t r e q u e s t b i t ( t m 3 r ) 3t i m e r 4 i n t e r r u p t r e q u e s t b i t ( t m 4 r ) 4 o s d i n t e r r u p t r e q u e s t b i t ( o s d r ) 5 v s y n c i n t e r r u p t r e q u e s t b i t ( v s c r ) 6 m u l t i - m a s t e r i 2 c - b u s i n t e r f a c e i n t e r r u p t r e q u e s t b i t ( i i c r ) 7 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 0 ] 0 ] 0 ] 0 ] 0 ] 0 ] 0 ] ] : 0 c a n b e s e t b y s o f t w a r e , b u t 1 c a n n o t b e s e t . ] 1 6 ] r r r r r r r r i n t 3 e x t e r n a l i n t e r r u p t r e q u e s t b i t ( i t 3 r ) 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d b 7b 6 b 5 b 4b 3 b 2 b 1 b 0 i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 ) [ a d d r e s s 0 0 f d bn a m e f u n c t i o n s a f t e r r e s e t rw i n t e r r u p t r e q u e s t r e g i s t e r 2 0 i n t 1 e x t e r n a l i n t e r r u p t r e q u e s t b i t ( i t 1 r ) 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 1 2 s e r i a l i / o i n t e r r u p t r e q u e s t b i t ( s 1 r ) 3 4 f ( x i n ) / 4 0 9 6 i n t e r r u p t r e q u e s t b i t ( m s r ) 5 7 f i x t h i s b i t t o 0 . 0 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 ] : 0 c a n b e s e t b y s o f t w a r e , b u t 1 c a n n o t b e s e t . 0 0 ] 0 0 ] 0 ] 0 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 1 6 ] r r r r ] r r r w s p r i t e o s d i n t e r r u p t r e q u e s t b i t ( s p r ) 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 6 a - d c o n v e r s i o n i n t e r r u p t r e q u e s t b i t ( a d r ) 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 ] r n o t h i n g i s a s s i g n e d . t h i s b i t i s a w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . i n t 2 e x t e r n a l i n t e r r u p t r e q u e s t b i t ( i t 2 r ) ] 128 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 addresses 00fe 16 address 00ff 16 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) [ a d d r e s s 0 0 f e 1 6 ] bn a m ef u n c t i o n s rw i n t e r r u p t c o n t r o l r e g i s t e r 1 0 t i m e r 1 i n t e r r u p t e n a b l e b i t ( t m 1 e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 1 t i m e r 2 i n t e r r u p t e n a b l e b i t ( t m 2 e ) 2 t i m e r 3 i n t e r r u p t e n a b l e b i t ( t m 3 e ) 3 4 o s d i n t e r r u p t e n a b l e b i t ( o s d e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 0 0 0 0 0 rw rw rw rw rw r 7 t i m e r 4 i n t e r r u p t e n a b l e b i t ( t m 4 e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 5 v s y n c i n t e r r u p t e n a b l e b i t ( v s c e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 rw 6 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 rw a f t e r r e s e t i n t 3 e x t e r n a l i n t e r r u p t e n a b l e b i t ( i t 3 e ) m u l t i - m a s t e r i 2 c - b u s i n t e r f a c e i n t e r r u p t e n a b l e b i t ( i i c e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d w b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) [ a d d r e s s 0 0 f f 1 6 ] bn a m ef u n c t i o n s a f t e r r e s e t rw i n t e r r u p t c o n t r o l r e g i s t e r 2 0 i n t 1 e x t e r n a l i n t e r r u p t e n a b l e b i t ( i t 1 e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 1 i n t 2 e x t e r n a l i n t e r r u p t e n a b l e b i t ( i t 2 e ) 2 s e r i a l i / o i n t e r r u p t e n a b l e b i t ( s 1 e ) 3 4 f ( x i n ) / 4 0 9 6 i n t e r r u p t e n a b l e b i t ( m s e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 0 0 0 0 rw rw rw rw rw s p r i t e o s d i n t e r r u p t e n a b l e b i t ( s p e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 5 f i x t h i s b i t t o 0 . 0 r 6 a - d c o n v e r s i o n i n t e r r u p t e n a b l e b i t ( a d e ) 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d 0 rw 7 0 r n o t h i n g i s a s s i g n e d . t h i s b i t i s a w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . 0 w 129 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 address 021b 16 address 0241 16 address 0240 16 b 7b 6b 5b 4b 3b 2b 1b 0 r o m c o r r e c t i o n e n a b l e r e g i s t e r ( r c r ) [ a d d r e s s 0 2 1 b 1 6 ] b a f t e r r e s e t rw r o m c o r r e c t i o n e n a b l e r e g i s t e r 0 v e c t o r 1 e n a b l e b i t ( r c r 0 ) n a m ef u n c t i o n s 0 : d i s a b l e d 1 : e n a b l e d 0 rw 1 v e c t o r 2 e n a b l e b i t ( r c r 1 ) 0 : d i s a b l e d 1 : e n a b l e d 0 rw 0 3 t o 7 f i x t h e s e b i t s t o 0 . 0 rw 0 0 0 0 2 v e c t o r 3 e n a b l e b i t ( r c r 2 ) 0 : d i s a b l e d 1 : e n a b l e d 0 rw b 7b 6b 5b 4b 3b 2b 1b 0 l e f t b o r d e r c o n t r o l r e g i s t e r ( l b r ) [ a d d r e s s 0 2 4 0 1 6 ] bn a m ef u n c t i o n s l e f t b o r d e r c o n t r o l r e g i s t e r c o n t r o l b i t s o f l e f t b o r d e r ( l b r 0 t o l b r 6 ) 0 t o 6 l e f t b o r d e r p o s i t i o n = t d e f 4 + 4 t o s c 5 n + 1 t o s c 5 w h ( n : s e t t i n g v a l u e , t d e f 4 : 4 t o s c , t o s c : o s d o s c i l l a t i o n c y c l e , w h : v a l u e ( 0 t o 3 ) o f w i n d o w h o r i z o n t a l p o s i t i o n m i n u t e a d j u s t m e n t b i t ) n o t h i n g i s a s s i g n e d . t h i s b i t i s w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s i n d e t e r m i n a t e . 7 a f t e r r e s e t r w 0 rw 0r n o t e : s e t v a l u e s f i t f o r l b r r b r . b 7b 6b 5b 4b 3b 2b 1b 0 r i g h t b o r d e r c o n t r o l r e g i s t e r ( r b r ) [ a d d r e s s 0 2 4 1 1 6 ] bn a m ef u n c t i o n s r i g h t b o r d e r c o n t r o l r e g i s t e r c o n t r o l b i t s o f l e f t b o r d e r ( r b r 0 t o r b r 6 ) 0 t o 6 n o t h i n g i s a s s i g n e d . t h i s b i t i s w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s i n d e t e r m i n a t e . 7 a f t e r r e s e t r w 0 rw 0r n o t e : s e t v a l u e s f i t f o r l b r r b r . r i g h t b o r d e r p o s i t i o n = t d e f 4 + 4 t o s c 5 n + 1 t o s c 5 w h ( n : s e t t i n g v a l u e , t d e f 4 : 4 t o s c , t o s c : o s d o s c i l l a t i o n c y c l e , w h : v a l u e ( 0 t o 3 ) o f w i n d o w h o r i z o n t a l p o s i t i o n m i n u t e a d j u s t m e n t b i t ) 130 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 address 0245 16 b 7b 6b 5b 4b 3b 2b 1b 0 t o p b o r d e r c o n t r o l r e g i s t e r ( t b r ) [ a d d r e s s 0 2 4 5 1 6 ] bn a m ef u n c t i o n s a f t e r r e s e t rw t o p b o r d e r c o n t r o l r e g i s t e r 0 t o 7 c o n t r o l b i t s o f t o p b o r d e r ( t b r 0 t o t b r 7 ) t o p b o r d e r p o s i t i o n = h d e f + h 5 n ( n : s e t t i n g v a l u e , h d e f : 1 7 h , h : h s y n c ) i n d e t e r m i n a t e rw n o t e s 1 : s e t v a l u e s e x c e p t 0 0 1 6 t o t b r . 2 : s e t v a l u e s f i t f o r t b r b b r . b 7b 6b 5b 4b 3b 2b 1b 0 b o t t o m b o r d e r c o n t r o l r e g i s t e r ( b b r ) [ a d d r e s s 0 2 4 6 1 6 ] bn a m ef u n c t i o n sa f t e r r e s e trw b o t t o m b o r d e r c o n t r o l r e g i s t e r 0 t o 7 c o n t r o l b i t s o f b o t t o m b o r d e r ( b b r 0 t o b b r 7 ) i n d e t e r m i n a t e rw b o t t o m b o r d e r p o s i t i o n = h d e f + h 5 n ( n : s e t t i n g v a l u e , h d e f : 1 7 h , h : h s y n c ) n o t e s 1 : s e t v a l u e s e x c e p t 0 0 1 6 t o b b r . 2 : s e t v a l u e s f i t f o r t b r b b r . address 0246 16 131 single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers rev. 1.0 21. package outline sdip42-p-600-1.78 weight(g) C jedec code 4.1 eiaj package code lead material alloy 42/cu alloy 42p4b plastic 42pin 600mil sdip symbol min nom max a a 2 b b 1 b 2 c e d l dimension in millimeters a 1 0.51 ?.8 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 36.5 36.7 36.9 12.85 13.0 13.15 1.778 15.24 3.0 0 e15 e e 5.5 e e 1 42 22 21 1 e c e 1 a 2 a 1 b b 1 b 2 e la seating plane d single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller m37225m6Cxxxsp, m37225m8Cxxxsp m37225ecsp mitsubishi microcomputers ? 1999 mitsubishi electric corp. new publication, effective sep. 1999. specifications subject to change without notice. notes regarding these materials ? these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product b est suited to the customers application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. ? mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-partys rights, origina ting in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. ? all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents inf ormation on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that c ustomers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assu mes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubish i semiconductor home page (http://www.mitsubishichips.com). ? when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. ? mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used und er circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herei n for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. ? the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these m aterials. ? if these products or technologies are subject to the japanese export control restrictions, they must be exported under a licen se from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. ? please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further detai ls on these materials or the products contained therein. keep safety first in your circuit designs! ? mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with a ppropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. head office: 2-2-3, marunouchi, chiyoda-ku, tokyo 100-8310, japan rev. rev. no. date 1.0 first edition 9909 revision description revision description list (1/1) M37225M6-XXXSP, m37225m8-xxxsp m37225ecsp (rev.1.0) tentative specifications |
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